NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 463

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10—Intel
10.1.3
Table 354. Offset 04 - 05h: CMD—Command Register (USB—D29:F0/F1)
November 2007
Order Number: 300641-004US
15:1
Bits
Default Value:
0
9
8
7
6
5
4
3
2
1
0
I/O Space Enable (IOSE)
Device:
®
Offset:
Postable Memory Write
Memory Space Enable
Parity Error Response
Special Cycle Enable
6300ESB ICH
VGA Palette Snoop
Wait Cycle Control
Bus Master Enable
Fast Back-to-back
Enable (PMWE)
SERR# Enable
Enable (FBE)
Offset 04 - 05h: CMD—Command Register
(USB—D29:F0/F1)
Reserved
29
04-05h
0000h
Name
(BME)
(MSE)
(SCE)
Reserved.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
When set, the Intel
the PCI bus for USB transfers.
Reserved as ‘0’.
This bit controls access to the I/O space registers.
0 = Disable
1 = Enable accesses to the USB I/O registers. The Base
Address register for USB should be programmed before
this bit is set.
®
6300ESB ICH may act as a master on
Description
Attribute:
Function:
Size:
0/1
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
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