NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 411

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.8.3.12 ALT_GP_SMI_STS—Alternate GPI SMI Status Register
Table 295. ALT_GP_SMI_STS—Alternate GPI SMI Status Register
8.8.3.13 MON_SMI—Device Monitor SMI Status and Enable Register
Table 296. MON_SMI—Device Monitor SMI Status and Enable Register
November 2007
Order Number: 300641-004US
15:0
15:1
11:8
Bits
Bits
Default Value:
Default Value:
7:0
I/O Address:
I/O Address:
2
Lockable:
Lockable:
®
Note: Usage: ACPI or Legacy.
Note: Usage: Legacy only.
Device:
Device:
6300ESB ICH
DEV[7:4]_TRAP_STS
DEV[7:4]_TRAP_EN
Reserved
31
PMBASE +3Ah
0000h
No
Name
31
PMBASE +40h
0000h
No
Name
These bits report the status of the corresponding GPIs. 1 =
active, 0 = inactive. These bits are sticky. When the
following conditions are true, an SMI# will be generated and
the GPE0_STS bit set:
All bits are in the resume well. Default for these bits is
dependent on the state of the GPI pins.
Bit 12 corresponds to Monitor 4, bit 13 corresponds to
Monitor 5 etc.
0 = SMI# was not caused by the associated device monitor.
1 = SMI# was caused by an access to the corresponding
Bit 8 corresponds to Monitor 4, bit 9 corresponds to Monitor 5
etc.
0 = Disable.
1 = Enables SMI# due to an access to the corresponding
Reserved.
• The corresponding bit in the ALT_GPI_SMI_EN register is
• The corresponding GPI must be routed in the GPI_ROUT
• The corresponding GPIO must be implemented.
set.
register to cause an SMI.
device monitor’s I/O range.
device monitor’s I/O range.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read-Only
16-bit
Resume
0
Read/Write, Read/Write Clear
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/WC
R/W
411
DS