NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 566

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 483. Intel
Table 484. Native Audio Bus Master Control Registers (Sheet 1 of 3)
Intel
DS
566
®
6300ESB I/O Controller Hub
Configuration (Sheet 2 of 2)
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the
AC’97 controller. Accesses to these registers do NOT cause the cycle to be forwarded
over the AC-link to the codec. S/W could access these registers as bytes, word, or
dWord quantities, but reads must not cross dWord boundaries.
In the case of split codec implementation, accesses to the different codecs are
differentiated by the controller by using address offsets 00h - 7Fh for the primary
codec, address offsets 80h - FFh for the secondary codec and address offsets 100h -
17Fh for the tertiary codec.
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to
the same global registers in the audio and modem I/O space. Therefore a read/write to
these registers in either audio or modem I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC’97 controller. The six
channels, PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their
own set of Bus Mastering registers. The following register descriptions apply to all six
channels. The register definition section titles use a generic “x_” in front of the register
to indicate that the register applies to all six channels. The naming prefix convention
used in
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel.
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
NOTES:
(Codec ID =00)
Offset
1. Software should not try to access reserved registers.
2. Primary Codec ID cannot be changed. Secondary codec ID may be changed through bits 1:0
3. The tertiary offset is only available through the memory space defined by the MMBAR
Primary Offset
00h
04h
05h
06h
08h
0Ah
0Bh
of configuration register 40h. Tertiary codec ID may be changed through bits 3:2 of
configuration register 40h.
register.
®
5Ah
7Ch
7Eh
Table 484
6300ESB I/O Controller Hub Audio Mixer Register
Mnemonic
PI_BDBAR
PI_PICB
PI_CIV
PI_PIV
PI_LVI
PI_SR
PI_CR
and in the register description I/O address is as follows:
Secondary Offset
(Codec ID =01)
PCM in Buffer Descriptor list Base Address
Register
PCM in Current Index Value
PCM in Last Valid Index
PCM in Status Register
PCM in Position in Current Buffer
PCM in Prefetched Index Value
PCM in Control Register
DAh
FCh
FEh
(Codec ID =10)
Tertiary Offset
Name
15Ah
17Ch
17Eh
Vendor Reserved
Vendor ID1
Vendor ID2
NAMBAR Exposed Registers
Order Number: 300641-004US
Intel
00000000h
(D31:F5)
Default
0003h
0000h
00h
00h
00h
00h
®
6300ESB ICH—13
November 2007
Access
R/W
R/W
R/W
R/W
RO
RO
RO