NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 723

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
Table 651. Divisor Latch Register High (DLH)
19.5.1.4 FIFO Operation
19.5.1.4.1 FIFO Interrupt Mode Operation
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Receiver Interrupt
When the Receive FIFO and receiver interrupts are enabled (FCR[0]=1 and IER[0]=1),
receiver interrupts occur as follows:
Character Timeout Interrupt
When the receiver FIFO and receiver time out interrupt are enabled, a character
timeout interrupt occurs when all of the following conditions exist:
The maximum time between a received character and a timeout interrupt is 160 ms at
300 baud with a 12-bit receive character (i.e., 1 start, 8 data, 1 parity, and 2 stop bits).
When a time out interrupt occurs, it is cleared and the timer is reset when the
processor reads one character from the receiver FIFO. If a timeout interrupt has not
occurred, the timeout timer is reset after a new character is received or after the
processor reads the receiver FIFO.
Transmit Interrupt
When the transmitter FIFO and transmitter interrupt are enabled (FCR[0]=1,
IER[1]=1), transmit interrupts occur as follows:
Divisor Latch Register High
DLH
read/write
Bit Number Bit Mnemonic
•
•
•
•
•
•
•
•
•
The receive data available interrupt is invoked when the FIFO has reached its
programmed trigger level. The interrupt is cleared when the FIFO drops below the
programmed trigger level.
The IIR receive data available indication also occurs when the FIFO trigger level is
reached, and like the interrupt, the bits are cleared when the FIFO drops below the
trigger level.
The receiver line status interrupt (IIR = C6H), as before, has the highest priority.
The receiver data available interrupt (IIR=C4H) is lower. The line status interrupt
occurs only when the character at the top of the FIFO has errors.
The data ready bit (DR in LSR register) is set to ’1’ as soon as a character is
transferred from the shift register to the Receive FIFO. This bit is reset to ’0’ when
the FIFO is empty.
At least one character is in the FIFO.
The last received character was longer than four continuous character times ago (if
2 stop bits are programmed the second one is included in this time delay).
The most recent processor read of the FIFO was longer than four continuous
character times ago.
The receiver FIFO trigger level is greater than one.
The Transmit Data Request interrupt occurs when the transmit FIFO is half empty
or more than half empty. The interrupt is cleared as soon as the Transmit Holding
7:0
BR[15:8]
Address:
Reset State:
Access:
High byte compare value to generate baud rate
Function
Base + 1 (DLAB=1)
00H
8-bit
Intel
®
6300ESB I/O Controller Hub
723
DS