NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 185

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 82.
5.14.3.6 Error Conditions
5.14.3.7 8237-Like Protocol
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Interrupt/Active Bit Interaction Definition
IDE devices are sector based mass storage devices. The drivers handle errors on a
sector basis; either a sector is transferred successfully or it is not. A sector is 512
bytes.
When the IDE device does not complete the transfer due to a hardware or software
error, the command will eventually be stopped by the driver setting Command Start bit
to zero when the driver times out the disk transaction. Information in the IDE device
registers help isolate the cause of the problem.
When the controller encounters an error while doing the bus master transfers, it will
stop the transfer (i.e., reset the Active bit in the Command register) and set the Error
bit in the Bus Master IDE Status register. The controller does not generate an interrupt
when this happens. The device driver may use device specific information (PCI
Configuration Space Status register and IDE Drive Register) to determine what caused
the error.
Whenever a requested transfer does not complete properly, information in the IDE
device registers (Sector Count) may be used to determine how much of the transfer
was completed and to construct a new PRD table to complete the requested operation.
In most cases the existing PRD table may be used to complete the operation.
8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins
familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/
write strobes. These pins have similar characteristics to their ISA counterparts in terms
of when data is valid relative to strobe edges, and the polarity of the strobes, however
the Intel
Interrup
0
1
1
0
t
®
6300ESB ICH does not use the 8237 for this mode.
Active
1
0
1
0
DMA transfer is in progress. No interrupt has been generated by the IDE
device.
The IDE device generated an interrupt. The controller exhausted the
Physical Region Descriptors. This is the normal completion case where the
size of the physical memory regions was equal to the IDE device transfer
size.
The IDE device generated an interrupt. The controller has not reached the
end of the physical memory regions. This is a valid completion case where
the size of the physical memory regions was larger than the IDE device
transfer size.
This bit combination signals an error condition. When the Error bit in the
status register is set, the controller has some problem transferring data
to/from memory. Specifics of the error have to be determined using bus-
specific information. When the Error bit is not set, then the PRD's
specified a smaller size than the IDE transfer size.
Description
Intel
®
6300ESB I/O Controller Hub
185
DS