NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 58

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 5.
Intel
DS
58
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6300ESB I/O Controller Hub
PCI Interface Signals (Sheet 2 of 3)
TRDY#
STOP#
PAR
PERR#
REQ[0:3]#
GNT[0:3]#
PCICLK
Signal
Name
Type
I/O
I/O
I/O
I/O
I
O
I
Target Ready: TRDY# indicates the Intel
complete the current data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is completed when both TRDY#
and IRDY# are sampled asserted. During a read, TRDY# indicates that
the Intel
During a write, it indicates the Intel
prepared to latch data. TRDY# is an input to the Intel
when the Intel
Intel
edge of PXPCIRST#. TRDY# remains tri-stated by the Intel
ICH until driven as a target.
Stop: STOP# indicates that the Intel
requesting an initiator to stop the current transaction. As an Initiator,
STOP# causes the Intel
STOP# is an output when the Intel
input when the Intel
from the leading edge of PXPCIRST#, and remains tri-stated until driven
by the Intel
Calculated/Checked Parity: PAR is “even” parity and is calculated on
36 bits – AD[31:0] plus C/BE[3:0]#. “Even” parity means that the
number of “1”s within the 36 bits plus PAR are counted and the sum is
always even. PAR is always calculated on 36 bits regardless of the valid
byte enables. PAR is generated for address and data phases, and is only
ensured to be valid one PCI clock after the corresponding address or data
phase. PAR is driven and tri-stated identically to the AD[31:0] lines,
except that PAR is delayed by exactly one PCI clock. PAR is an output
during the address phase (delayed one clock) for all Intel
initiated transactions. It is also an output during the data phase (delayed
one clock) when the Intel
transaction, and when it is the Target of a read transaction.
The Intel
Initiator of PCI read transactions and when it is the Target of PCI write
transactions. It also checks parity on the address phase when it is the
target of PCI transitions. If a parity error is detected, the Intel
ICH will set the appropriate internal status bits, and has the option to
generate an NMI# or SMI#.
Parity Error: Driven by an external PCI device when it receives data that
has a parity error. Driven by the Intel
parity error. The Intel
SMI# upon detecting a parity error (either detected internally or reported
via PERR# signal) when serving as an initiator.
PCI Requests: Supports up to 4 external masters on the PCI bus.
PCI Grants: Supports up to 4 external masters on the PCI bus.
NOTE: PCI Clock: 33 MHz clock. PCICLK provides timing for all
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6300ESB ICH is a Target. TRDY# is tri-stated from the leading
transactions on the PCI Bus, as well as many units inside the
Intel
This clock can be stopped in S1 or S3, S4, or S5 states. This signal
is not
5 V tolerant.
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6300ESB ICH, as a Target, has placed valid data on AD[31:0].
6300ESB ICH checks parity on the data phase when it is the
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6300ESB ICH as a slave.
6300ESB ICH.
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6300ESB ICH is the Initiator and an output when the
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6300ESB ICH is an Initiator. STOP# is tri-stated
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6300ESB ICH can either generate an NMI# or
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6300ESB ICH to stop the current transaction.
6300ESB ICH is the Initiator of a PCI write
Description
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6300ESB ICH is a Target and an
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6300ESB ICH, as a Target is
6300ESB ICH, as a Target, is
6300ESB ICH when it detects a
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6300ESB ICH’s ability to
Order Number: 300641-004US
Intel
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6300ESB ICH
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6300ESB ICH—3
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6300ESB ICH
November 2007
6300ESB
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6300ESB