NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 570

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
570
15:5
Bits
Default Value:
I/O Address:
4
3
2
1
0
®
Table 488. x_SR—Status Register
6300ESB I/O Controller Hub
Lockable:
Device:
Interrupt Status (BCIS)
DMA Controller Halted
Completion Interrupt
Current Equals Last
FIFO Error (FIFOE)
Buffer Completion
Last Valid Buffer
Valid (CELV)
Reserved
(LVBCI)
31
NABMBAR + 06h (PISR), NABMBAR + 16h
(POSR), NABMBAR + 26h (MCSR), MBBAR
+ 46h (MC2SR), MBBAR + 56h (PI2SR),
MBBAR + 66h (SPSR)
0001h
No
Name
(DCH)
Reserved.
0 = Cleared by writing a “1” to this bit position.
1 = FIFO error occurs.
PISR Register: FIFO error indicates a FIFO overrun. The
FIFO pointers don't increment; the incoming data is not
written into the FIFO, thus is lost.
POSR Register: FIFO error indicates a FIFO underrun. The
sample transmitted in this case should be the last valid
sample.
The Intel
or overrun occurs when there are more valid buffers to
process.
0 = Cleared by writing a “1” to this bit position.
1 = Set by the hardware after the last sample of a buffer has
0 = Cleared by writing a “1” to this bit position.
1 = Last valid buffer has been processed. It remains active
0 = Cleared by hardware when controller exits state (i.e.,
1 = Current Index is equal to the value in the Last Valid Index
0 = Running.
1 = Halted. This could happen because of the Start/Stop bit
been processed, AND if the Interrupt on Completion
(IOC) bit is set in the command byte of the buffer
descriptor. It remains active until cleared by software.
until cleared by software. This bit indicates the
occurrence of the event signified by the last valid buffer
being processed. Thus, this is an event status bit that
may be cleared by software once this event has been
recognized. This event will cause an interrupt when the
enable bit in the Control Register is set. The interrupt is
cleared when the software clears this bit.
In the case of Transmits (PCM out, Modem out) this bit is
set after the last valid buffer has been fetched, not after
transmitting it. In the case of Receives, this bit is set
after the data for the last buffer has been written to
memory.
until a new value is written to the LVI register.)
Register, and the buffer pointed to by the CIV has been
processed (i.e., after the last valid buffer has been
processed). This bit is very similar to bit 2, except this bit
reflects the state rather than the event. This bit reflects
the state of the controller and remains set until the
controller exits this state.
being cleared and the DMA engines are idle, or it could
happen once the controller has processed the last valid
buffer.
®
6300ESB ICH will set the FIFOE bit if the underrun
Description
Power Well:
Attribute:
Function:
Size:
5
Read/Write Clear, Read-Only
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—13
November 2007
Access
R/WC
R/WC
R/WC
RO
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RO