NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 194

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
194
Warning:As the timer period approaches zero, the interrupts associated with the
®
6300ESB I/O Controller Hub
may pass the value before it reaches the register and the interrupt will be
missed.
All three timers support non-periodic mode.
Periodic Mode
Timer 0 is the only timer that supports periodic mode. When Timer 0 is set up for
periodic mode, the software writes a value into the timer’s comparator value register.
When the main counter value matches the value in the timer’s comparator value
register, an interrupt may be generated. The hardware will then automatically increase
the value in the comparator value register by the last value written to that register.
To make the periodic mode work properly, the main counter is typically written with a
value of zero so that the first interrupt occurs at the right point for the comparator.
When the main counter is not set to zero, interrupts may not occur as expected.
During run-time, the value in the timer’s comparator value register may be read by
software to find out when the next periodic interrupt will be generated (not the rate at
which it generates interrupts). Software is expected to remember the last value written
to the comparator’s value register (the rate at which interrupts are generated).
When software wants to change the periodic rate, it should write a new value to the
comparator value register. At the point when the timer’s comparator indicates a match,
this new value will be added to derive the next matching point.
When the software resets the main counter, the value in the comparator’s value
register needs to be reset as well. This may be done by setting the
TIMER0_VAL_SET_CNF bit. Again, to avoid race conditions, this should be done with
the main counter halted. See
bits details.
The following usage model is expected:
periodic timer may not get completely serviced before the next timer match
occurs. Interrupts may get lost and/or system performance may be degraded
in this case.
The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-
bit write in a 32-bit environment except when only the periodic rate is being changed
during run-time. When the actual Timer 0 Comparator Value needs to be reinitialized,
the following software solution will always work regardless of the environment:
1. Software clears the ENABLE_CNF bit to prevent any interrupts
2. Software Clears the main counter by writing a value of 00h to it.
3. Software sets the TIMER0_VAL_SET_CNF bit.
4. Software writes the new value in the TIMER0_COMPARATOR_VAL register
5. Software sets the ENABLE_CNF bit to enable interrupts.
1. Set TIMER0_VAL_SET_CNF bit
2. Set the lower 32 bits of the Timer0 Comparator Value register
3. Set TIMER0_VAL_SET_CNF bit
4. Set the upper 32 bits of the Timer0 Comparator Value register
Section 15, “Multimedia Timer Registers”
Order Number: 300641-004US
Intel
for register and
®
6300ESB ICH—5
November 2007