NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 637

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17—Intel
17.1.11 Offset 40 - 41h: ABAR—APIC1 Alternate Base
Table 568. Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register
17.1.12 Offset 44 - 47h: MBAR—APIC1 Memory Base
November 2007
Order Number: 300641-004US
13:1
11:8
Bits
Default Value:
7:4
3:0
15
14
2
Lockable:
Note: This register contains an alternate base address in the legacy APIC range. This range
Note: On downstream writes, only ABAR + Offset 40h (EOI) is claimed. On upstream cycles,
Note: This register contains the APIC1 Base Address for the memory space.
Device:
®
Offset:
Base Address [19:16]
Base Address [15:12]
Base Address [11:8]
6300ESB ICH
BIE: Boot Interrupt
EN: Enable
Address Register (APIC1—D29:F5)
may coexist with the BAR register range. This range is needed for OSs that support the
APIC but do not yet support remapping the APIC anywhere in the 4 Gbyte address
space.
only ABAR + offset 20h are claimed.
(APIC1—D29:F5)
Register (APIC1—D29:F5)
Reserved
(XBAD)
(ZBAD)
(YBAD)
Enable
29
40-41h
8000h
No
Name
When set, the range FECX_YZ00 to FECX_YZFF is enabled as
an alternate access method to the IOxAPIC registers. Bits
‘XYZ’ are defined below.
0 = Boot interrupt is enabled.
1 = Boot interrupt is disabled.
NOTE: For details on the Boot interrupt, see
Reserved.
These bits determine the high order bits of the I/O APIC
address map. When a memory address is recognized by the
Intel
the Intel
the internal I/O APIC1.
These bits determine the low order bits of the I/O APIC
address map. When a memory address is recognized by the
Intel
the Intel
the internal I/O APIC1.
These bits determine the low order bits of the I/O APIC
address map. When a memory address is recognized by the
Intel
the Intel
the internal I/O APIC1
®
®
®
6300ESB ICH that matches FECX_YZ00 or FECX_YZ10,
6300ESB ICH that matches FECX_YZ00 or FECX_YZ10,
6300ESB ICH that matches FECX_YZ00 or FECX_YZ10,
“Boot
®
®
®
6300ESB ICH will respond to the cycle and access
6300ESB ICH will respond to the cycle and access
6300ESB ICH will respond to the cycle and access
Interrupt”.
Power Well:
Description
Attribute:
Function:
Size:
5
Read/Write
16-bit
Core
Section 5.7.3,
Intel
®
6300ESB I/O Controller Hub
Access
RW
RO
637
DS