NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 355

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.2.11
Table 230. DMA_WRMSK—DMA Write All Mask Register
I
8.3
Table 231. Timer I/O Registers
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:4
3:0
I/O Address:
Lockable:
®
Device:
6300ESB ICH
Channel Mask Bits
DMA_WRMSK—DMA Write All Mask Register
Timer I/O Registers
Reserved
Port
31
Ch. #0-3 = 0Fh;
Ch. #4-7 = DEh
0000 1111
No
Name
40h
41h
42h
43h
Aliases
50h
51h
52h
53h
Reserved. Must be 0.
This register permits all four channels to be simultaneously
enabled/disabled instead of enabling/disabling each channel
individually, as is the case with the Mask Register - Write
Single Mask Bit. In addition, this register has a read path to
allow the status of the channel mask bits to be read. A
channel's mask bit is automatically set to 1 when the Current
Byte/Word Count Register reaches terminal count (unless the
channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s).
Setting the bit(s) to a 0 enables the corresponding DREQ(s).
Bits [3:0] are set to 1 upon part reset or Master Clear. When
read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask
status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0-3 due to
Counter 0 Interval Time Status Byte
Format
Counter 0 Counter Access Port Register
Counter 1 Interval Time Status Byte
Format
Counter 1 Counter Access Port Register
Counter 2 Interval Time Status Byte
Format
Counter 2 Counter Access Port Register
Timer Control Word Register
Timer Control Word Register Read Back
Counter Latch Command
the cascade of channel’s 0 - 3 through channel 4.
Register Name/Function
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
0XXXXXXXb
0XXXXXXXb
0XXXXXXXb
XXXXXXX0b
Undefined
Undefined
Undefined
Undefined
Intel
Default
Value
X0h
®
6300ESB I/O Controller Hub
Access
Type
R/W
R/W
R/W
WO
WO
WO
RO
RO
RO
R/W
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