NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 473

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10—Intel
10.2
Table 370. USB I/O Registers
10.2.1
November 2007
Order Number: 300641-004US
Note: The Command Register indicates the command to be executed by the serial bus host
®
6300ESB ICH
USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub
ports function so that, on read-back, they reflect the current state of the port, and not
necessarily the state of the last write to the register. This allows the software to poll the
state of the port and wait until it is in the proper state before proceeding. A Host
Controller Reset, Global Reset, or Port Reset will immediately terminate a transfer on
the affected ports and disable the port. This affects the USBCMD register, bit [4] and
the PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
Offset 00 - 01h: USBCMD—USB Command Register
controller. Writing to the register causes a command to be executed. The table
following the bit description provides additional information on the operation of the
Run/Stop and Debug bits.
NOTE: These registers are WORD writable only. Byte writes to these registers have
Offset
08-0B
0D-0F
00-01
02-03
04-05
06-07
10-11
12-13
14-17
0C
unpredictable effects.
FRBASEADD
Mnemonic
PORTSC0
PORTSC1
USBINTR
USBCMD
SOFMOD
USBSTA
FRNUM
USB Command Register
USB Status Register
Interrupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Reserved
Port 0 Status/Control
Port 1 Status/Control
Reserved
Register
Undefined
Default
Intel
0000h
0020h
0000h
0000h
0080h
0080h
40h
0
0
®
6300ESB I/O Controller Hub
R/W (see NOTE:)
R/WC (see
R/WC (see
NOTE:)
NOTE:)
Type
R/W*
R/WC
R/W
R/W
R/W
RO
RO
473
DS