NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 218

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 105. USB Legacy Keyboard/Mouse Control Register Bit Implementation
Intel
DS
218
NOTE: If bit 7 of the Extended Test Mode Register 1 (D31:F0, offset F4h ETR1, section 9.1.36) is set. Port 60/64h
Bit
#
4
3
2
1
0
®
6300ESB I/O Controller Hub
SMI on USB IRQ
SMI on Port 64
Writes Enable
SMI on Port 64
Reads Enable
SMI on Port 60
Writes Enable
SMI on Port 60
Reads Enable
Note: The scheme described below assumes that the keyboard controller (8042 or
Reads and Writes from an external PCI agent will not affect set bits 8-11 and will not cause an SMI
independent of the setting of bits 0-3
Bit Name
(Sheet 2 of 2)
equivalent) is on the LPC bus.
This legacy operation is performed through SMM space.
Figure 21
64W) is available in the Status Register. Since the enable is after the latch, it is possible
to check for other events that didn't necessarily cause an SMI. It is the software's
responsibility to logically AND the value with the appropriate enable bits.
Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY#
goes active) to ensure that the processor doesn't complete the cycle before the SMI is
observed. This method is used on MPIIX and has been validated.
The logic will also need to block the accesses to the 8042. When there is an external
8042, then this is simply accomplished by not activating the 8042 CS. This is simply
done by logically ANDing the four enables (60R, 60W, 64R, 64W) with the four types of
accesses to determine when 8042CS should go active. An additional term is required
for the “Pass-through” case.
The state table for the diagram is shown in
Independent
Enable
Separate
enables ORed
together
Separate
enables OR’ed
together
Separate
enables OR’ed
together
Separate
enables OR’ed
together
shows the Enable and Status path. The latched SMI source (60R, 60W, 64R,
Summary
Each bit provides individual host control.
Each bit enables SMI generation when the corresponding bit 11 is
set. When bit 11 is implemented as a shared/aliased bit across all
functions, then the bit 3’s from all three controllers are ORed
together and used to enable the SMI based on bit 11.
Each bit enables SMI generation if the corresponding bit 10 is set. If
bit 10 is implemented as a shared/aliased bit across all functions,
then the bit 2's from all three controllers are OR'ed together and
used to enable the SMI based on bit 10.
Each bit enables SMI generation if the corresponding bit 9 is set. If
bit 9 is implemented as a shared/aliased bit across all functions, then
the bit 1's from all three controllers are OR'ed together and used to
enable the SMI based on bit 9.
Each bit enables SMI generation if the corresponding bit 8 is set. If
bit 8 is implemented as a shared/aliased bit across all functions, then
the bit 0's from all three controllers are OR'ed together and used to
enable the SMI based on bit 8.
Table
106.
Details
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007