NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 535

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12—Intel
November 2007
Order Number: 300641-004US
Bits
Default Value:
7
6
5
4
3
Table 440. Offset 00h: HST_STS—Host Status Register (Sheet 1 of 2)
Device:
®
Offset:
6300ESB ICH
BYTE_DONE_STS
SMBALERT_STS
INUSE_STS
BUS_ERR
FAILED
31
00h
00h
Name
This bit will be set to ’1’ when the host controller has received
a byte (for Block Read commands) or when it has completed
transmission of a byte (for Block Write commands) when the
32-byte buffer is not being used. Note that this bit will be set
even on the last byte of the transfer. Software clears the bit
by writing a ’1’ to the bit position. This bit is not set when
transmission is due to an external LAN Controller interface
heartbeat.
This bit has no meaning for block transfers when the 32-byte
buffer is enabled.
NOTE: When the last byte of a block message is received, the
This bit is used as semaphore among various independent
software threads that may need to use the Intel
ICH’s SMBus logic and has no other effect on hardware.
0 = After a full PCI reset, a read to this bit returns a ‘0’.
1 = After the first read, subsequent reads will return a ‘1’. A
0 = Interrupt or SMI# was not generated by SMBALERT#.
1 = The source of the interrupt or SMI# was the SMBALERT#
When the signal is programmed as a GPIO, this bit will never
be set.
0 = Cleared by writing a ’1’ to the bit position.
1 = The source of the interrupt or SMI# was a failed bus
0 = Cleared by writing a ’1’ to the bit position.
1 = The source of the interrupt of SMI# was a transaction
write of a ’1’ to this bit will reset the next read value to
‘0’. Writing a ’0’ to this bit has no effect. Software may
poll this bit until it reads a 0 and will then own the usage
of the host controller.
signal. This bit is only cleared by software writing a ’1’ to
the bit position or by RSMRST# going low.
transaction. This bit is set in response to the KILL bit
being set to terminate the host transaction.
collision.
host controller will set this bit. However, it will not
immediately set the INTR bit (bit 1 in this register).
When the interrupt handler clears the
BYTE_DONE_STS bit, another interrupt may be
generated if the INTR bit is set. Thus, for a block
message of n bytes, the Intel
generate n+1 interrupts. The interrupt handler needs
to be implemented to handle these cases.
Description
Attribute:
Function:
Size:
®
3
Read/Write Clear
8-bit
6300ESB ICH will
®
Intel
6300ESB
®
6300ESB I/O Controller Hub
(special)
Access
R/WC
R/WC
R/WC
R/WC
R/WC
535
DS