NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 429

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.10.5
Table 317. Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register
November 2007
Order Number: 300641-004US
7, 25
31:2
24:2
17:0
28:2
19:1
Bits
Default Value:
26,
9,
0,
8
Lockable:
®
Device:
Offset:
6300ESB ICH
GP_BLINK[n]
GP_BLINK[n]
Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink
Enable Register
Reserved
31
GPIOBASE +18h
00000000h
No
Name
Reserved.
The setting of these bits will have no effect when the
corresponding GPIO is programmed as an input. These bits
correspond to GPIO that are in the Resume well, and will be
reset to their default values by RSMRST# or a write to the
CF9h register.
0 = The corresponding GPIO will function normally.
1 = When the corresponding GPIO is programmed as an
The setting of these bits will have no effect when the
corresponding GPIO is programmed as an input. These bits
correspond to GPIO that are in the Core well, and will be reset
to their default values by PXPCIRST#.
0 = The corresponding GPIO will function normally.
1 = When the corresponding GPIO is programmed as an
output, the output signal will blink at a rate of
approximately once per second. The high and low times
have approximately 0.5 seconds each. The GP_LVL bit is
not altered when this bit is set.
output, the output signal will blink at a rate of
approximately once per second. The high and low times
are approximately 0.5 seconds each. The GP_LVL bit is
not altered when this bit is set.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
See bit description
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
429
DS