NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 47

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
Revision History
November 2007
Order Number: 300641-004US
November
Date
2007
®
6300ESB ICH
Revision
004
• Included Specification Changes from specification update, version 011
• Included Specifications Clarifications from specification update, version 011
• Included Documentation Changes 2 to 13 from specification update, version
•
•
•
•
011
Table
to 6300ESB
Table
RSM_PWROK signals which do not exist in 6300ESB
Table
test mode.
Section 5.7
APIC0 registers are purely memory mapped.
—
—
— Section 5.11.1 and 5.11.6: Clarified wording regarding support of C2
—
— Section 5.7.1: Removed references to three wire APIC bus. 6300ESB
—
—
— Removed all references to Processor Speed Strapping. Processors used
—
—
—
—
—
—
— Changed all references to PCIRST# to PXPCIRST#
—
—
—
— Corrected Product Features section to show that PCI-X Rev 1.0 is
—
—
—
—
Figure
Table 727
to clarify which Vcc supplies apply to each
state for dual processors, dual core and processors with HyperThreading
Technology.
Table
does not support this feature.
Table
Table
power up or down together
in conjunction with 6300ESB do not use this feature.
Table
configured as native functions after a full reset.
Section
compatible.
Table
Section
multiple core configurations can generate Stop Grant cycles in the MCH
supports it.
Table
Section
Table
Figure
Table
supported
Table
Table
Table
Note at bottom of table.
Table
values
313: Removed GPO_TTL register listing. This register was not relevant
29,
731,
Figure 61
191: Remove incorrect references to TCO in Note
31: Moved Note 1 refernces from I/O to Memory cycles
727: Changed Note 2 to require that 3.3V and 1.5V rails must
319: Modified register defintions to reflect that signals are
635: Added % error rates.
568: Revised to allow bit column to align correctly.
317: Changed register deult value to 00000000h
28: Change GPIO[21] After Reset value to logic ‘1’
22: Correct V5REF definition
573: Correct indexes for Reserved Registers
581: Revised naming and definitions for bits 10:8 and 7:0. Added
728: Revised ‘SLP_S5# inactive to SLP_S4#’ parameter timing
Figure
and
61: Updated to replace V_CPU_IO with VccHI
5: Correct typo in diagram
19.1: Add Note to indicate that SIUs are not completely 16550
5.10.2.2: Changed to clarify where multiple processor or
22.2: Added Case temperature under Bias value
and
Section
66: Updated to correct timing requirements for entering
Table
and
Figure
8.5: Removed PCI register references for APIC0.
728: Updated t175, t176 & t184 timing definitions
Description
62: Removed references to LAN_RST and
Intel
®
6300ESB I/O Controller Hub
DS
47