NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 199

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
5—Intel
Table 88.
November 2007
Order Number: 300641-004US
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6300ESB ICH
TD Control and Status (Sheet 2 of 3)
Bit
21
20
19
17
23
22
18
Active: For Intel
“Data Transfers to/from Main
0 = When the transaction associated with this descriptor is completed, the Intel
1 = Set to 1 by software to enable the execution of a message transaction by the Intel
Stalled:
1 = Set to a 1 by the Intel
Data Buffer Error (DBE):
1 = Set to a 1 by the Intel
Babble Detected (BABD):
1 = Set to a 1 by the Intel
Negative Acknowledgment (NAK) Received (NAKR):
1 = Set to a 1 by the Intel
CRC/time-out error (CRC_TOUT):
1 = Set to a 1 by the Intel
During a status update in the case that no response is received from the target device/
endpoint within the time specified by the protocol chapter of the USB specification.
During a status update when a Cyclic Redundancy Check (CRC) error is detected during
the transaction associated with this transfer descriptor.
In the transmit case (OUT or SETUP Command), this is in response to the Intel
6300ESB ICH detecting a timeout from the target device/endpoint.
In the receive case (IN Command), this is in response to the Intel
checker circuitry detecting an error on the data received from the device/endpoint or a
NAK or STALL handshake being received in response to a SETUP transaction.
Bit stuff Error (BSE):
1 = This bit is set to a 1 by the Intel
6300ESB ICH sets this bit to 0 indicating that the descriptor should not be executed
when it is next encountered in the schedule. The Active bit is also set to 0 when a
stall handshake is received from the endpoint.
6300ESB ICH.
serious error has occurred at the device/endpoint addressed by this TD. This may
be caused by babble, the error counter counting down to zero, or reception of the
STALL handshake from the device during the transaction. Any time that a
transaction results in the Stalled bit being set, the Active bit is also cleared (set to
0). When a STALL handshake is received from a SETUP transaction, a time-out
error will also be reported.
Intel
(overrun) or is unable to supply data fast enough during transmission (underrun).
When this occurs, the actual length and Max Length field of the TD will not match.
In the case of an underrun, the Intel
(thus invalidating the data at the endpoint) and leave the TD active (unless error
count reached zero). When an overrun condition occurs, the Intel
will force a timeout condition on the USB, invalidating the transaction at the source.
detected during the transaction generated by this descriptor. Babble is unexpected
bus activity for more than a preset amount of time. In addition to setting this bit,
the Intel
is considered a fatal error for that transfer, setting the ”STALLED” bit to a 1 insures
that no more transactions occur as a result of this descriptor. Detection of babble
causes immediate termination of the current frame. No further TDs in the frame are
executed. Execution resumes with the next frame list index.
6300ESB ICH receives a “NAK” packet during the transaction generated by this
descriptor. When a NAK handshake is received from a SETUP transaction, a time-
out error will also be reported.
that the receive data stream contained a sequence of more than 6 ones in a row.
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6300ESB ICH is unable to keep up with the reception of incoming data
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6300ESB ICH also sets the ”STALLED” bit (bit 22) to a 1. Since “babble”
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6300ESB ICH schedule execution operations, see
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6300ESB ICH during status updates to indicate that a
6300ESB ICH during status update to indicate that the
6300ESB ICH during status update when “babble” is
6300ESB ICH during status update when the Intel
6300ESB ICH as follows:
Memory”, Data Transfers to/from Main Memory.
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Description
6300ESB ICH during status update to indicate
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6300ESB ICH will transmit an incorrect CRC
Intel
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6300ESB I/O Controller Hub
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6300ESB ICH’s CRC
Section 5.17.3,
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6300ESB ICH
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DS

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