NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 748

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20.1.18 Offset 3Dh: INTR_PN—Interrupt Pin Register
20.1.19 Offset 40 - 41h: IDE_TIMP—Primary IDE Timing
Intel
DS
748
13:1
Bits
Bits
Default Value:
Default Value:
7:3
2:0
15
14
2
®
Table 678. Offset 3Dh: INTR_PN—Interrupt Pin Register (SATA–D31:F2)
Table 679. Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register (SATA–
6300ESB I/O Controller Hub
Note: This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
Device:
Device:
Offset:
Offset:
Drive 1 Timing Register
IORDY Sample Point
IDE Decode Enable
Enable (SITRE)
Interrupt Pin
(SATA–D31:F2)
Register
(SATA–D31:F2)
transfers. It also controls operation of the buffer for PIO transfers.
D31:F2)
Reserved
(Sheet 1 of 2)
31
3Dh
01h
Name
31
Primary:
Secondary: 42-43h
0000h
Name
(IDE)
(ISP)
40-41h
Reserved.
The value of 01h indicates to “software” that the Intel
6300ESB ICH will drive INTA#. Note that this is only used in
native mode. Also note that the routing to the internal
interrupt controller does not necessarily relate to the value in
this register.
Individually enable/disable the Primary or Secondary decode.
0 = Disable.
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and
native-Mode decoding.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE
The setting of these bits determine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY
sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
associated Command Blocks (1F0-1F7h for primary, 170-
177h for secondary) and Control Block (3F6h for primary
and 376h for secondary).
Timing register for drive 1
®
6300ESB ICH to decode the
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read-Only
8-bit
2
Read/Write
16-bit
Order Number: 300641-004US
®
Intel
®
6300ESB ICH—20
November 2007
Access
Access
R/W
R/W
RO