EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 215

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions
clock and the input clock buffer affect the output DCD.
Figure 5–9. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
IOE
INPUT
clk
VCC
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–80
derivation for different I/O standards on Stratix II devices. Examples are
also provided that show how to calculate DCD as a percentage.
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 1
of 2)
Row I/O Output
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
Altera Corporation
April 2011
(Figure
5–9). Therefore, any distortion on the input
V
DFF
CC
PRN
D
Q
CLRN
inst2
DFF
PRN
GND
D
Q
NOT
CLRN
inst8
inst3
through
5–87
give the maximum DCD in absolution
Note (1)
Maximum DCD for Non-DDIO Output
Standard
-3 Devices
245
125
105
DC & Switching Characteristics
OUTPUT
output
-4 & -5 Devices
Unit
275
ps
155
ps
135
ps
Stratix II Device Handbook, Volume 1
5–79

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