EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
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Table 2–16. Stratix II Supported I/O Standards (Part 2 of 2)
I/O Standard
SSTL-2 Class I and II
Voltage-referenced
Notes to
Table
2–16:
(1)
This I/O standard is only available on input and output column clock pins.
(2)
This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9,10, 11, and 12.
(3)
V
is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 9, 10, 11, and 12).
CCIO
The clock input pins supporting LVDS on banks 3, 4, 7, and 8 use V
dependency on the V
level of the bank.
CCIO
(4)
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
f
For more information on I/O standards supported by Stratix II I/O
banks, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
Stratix II devices contain eight I/O banks and four enhanced PLL external
clock output banks, as shown in
right and left of the device contain circuitry to support high-speed
differential I/O for LVDS and HyperTransport inputs and outputs. These
banks support all Stratix II I/O standards except PCI or PCI-X I/O pins,
and SSTL-18 Class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
Altera Corporation
May 2007
Input Reference
Type
Voltage (V
) (V)
REF
1.25
CCINT
Figure
Stratix II Architecture
Output Supply
Board Termination
Voltage (V
) (V)
Voltage (V
) (V)
CCIO
TT
2.5
1.25
for LVDS input operations and have no
2–57. The four I/O banks on the
Stratix II Device Handbook, Volume 1
2–87