EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
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TriMatrix Memory
Figure 2–22. M4K RAM Block LAB Row Interface
C4 Interconnect
16
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
M4K RAM Block Local
Interconnect Region
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
You cannot use an initialization file to initialize the contents of an M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
2–34
Stratix II Device Handbook, Volume 1
36
dataout
M4K RAM
Block
datain
byte
control
enable
signals
clocks
address
LAB Row Clocks
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
R4 Interconnect
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
6
Altera Corporation
May 2007