EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
EP2S90F1020I4N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
Page 65/238

Download datasheet (3Mb)Embed
PrevNext
The Stratix II clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state thereby reducing the overall
power consumption of the device.
The global and regional clock networks can be powered down statically
through a setting in the configuration (.sof or .pof) file. Clock networks
that are not used are automatically powered down through configuration
bit settings in the configuration file generated by the Quartus II software.
The dynamic clock enable/disable feature allows the internal logic to
control power up/down synchronously on GCLK and RCLK nets and
PLL_OUT pins. This function is independent of the PLL and is applied
directly on the clock network or PLL_OUT pin, as shown in
through 2–39.
1
Enhanced & Fast PLLs
Stratix II devices provide robust clock management and synthesis using
up to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features such as clock switchover,
spread-spectrum clocking, reconfigurable bandwidth, phase control, and
reconfigurable phase shifting, the Stratix II device’s enhanced PLLs
provide you with complete control of clocks and system timing. The fast
PLLs provide general purpose clocking with multiplication and phase
shifting as well as high-speed outputs for high-speed differential I/O
support. Enhanced and fast PLLs work together with the Stratix II
high-speed I/O and advanced clock architecture to provide significant
improvements in system performance and bandwidth.
Altera Corporation
May 2007
The following restrictions for the input clock pins apply:
•
CLK0 pin -> inclk[0] of CLKCTRL
•
CLK1 pin -> inclk[1] of CLKCTRL
•
CLK2 pin -> inclk[0] of CLKCTRL
•
CLK3 pin -> inclk[1] of CLKCTRL
In general, even CLK numbers connect to the inclk[0] port of
CLKCTRL, and odd CLK numbers connect to the inclk[1] port
of CLKCTRL.
Failure to comply with these restrictions will result in a no-fit
error.
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Figures 2–37
2–57

Related parts for EP2S90F1020I4N

Part NumberDescriptionManufacturer Datasheet Request
DK-CYCII-2C20N  DK-CYCII-2C20N CYCLONE II STARTER KIT EP2C20N Altera
  EP1AGX50DF780I6 ALTERA Altera
  AN209 Altera Corporation
  EP610PC-35 CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP Altera Corporation
  EP610PC-15 CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP Altera Corporation
  EP610IPC-25 Altera Corporation
  EP610PC-30 CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP Altera Corporation
  EP220PC-10 High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns Altera Corporation
  EP220PC-7 High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns Altera Corporation
  EP220PC-12 Classic EPLD Altera Corporation
  EP220PC-10A High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns Altera Corporation
  P85C224-66 Altera Corporation
  EP320PC Altera Corporation
  EP2A15B724C7 Altera Corporation
  EP610PC-25T CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP Altera Corporation