EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 220

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N
Duty Cycle Distortion
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Notes
(1),
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
DDIO Column Output I/O
Standard
3.3/2.5 V
1.8 V
150
1.5-V LVCMOS
255
SSTL-2 Class I
175
SSTL-2 Class II
170
SSTL-18 Class I
155
SSTL-18 Class II
140
1.8-V HSTL Class I
150
1.8-V HSTL Class II
150
1.5-V HSTL Class I
150
1.5-V HSTL Class II
125
1.2-V HSTL
240
LVPECL
180
Notes to
Table
5–84:
(1)
Table 5–84
assumes the input clock has zero DCD.
(2)
The DCD specification is based on a no logic array noise condition.
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2)
Notes
(1),
DDIO Column Output I/O
Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
5–84
Stratix II Device Handbook, Volume 1
(2)
Clock Port (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
1.8/1.5 V
2.5 V
265
85
370
140
295
65
290
60
275
55
260
70
270
60
270
60
270
55
240
85
360
155
180
180
(2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
TTL/CMOS
3.3/2.5 V
1.8/1.5 V
440
495
390
450
375
430
325
385
430
490
355
410
350
405
1.2-V
Unit
SSTL/HSTL
HSTL
1.8/1.5 V
1.2 V
85
85
ps
140
140
ps
65
65
ps
60
60
ps
50
50
ps
70
70
ps
60
60
ps
60
60
ps
55
55
ps
85
85
ps
155
155
ps
180
180
ps
Unit
SSTL-2
SSTL/HSTL
2.5 V
1.8/1.5 V
170
160
ps
120
110
ps
105
95
ps
90
100
ps
160
155
ps
85
75
ps
80
70
ps
Altera Corporation
April 2011

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