EP2S90F1020I4N

Manufacturer Part NumberEP2S90F1020I4N
DescriptionIC STRATIX II FPGA 90K 1020-FBGA
ManufacturerAltera
SeriesStratix® II
EP2S90F1020I4N datasheet
 

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells90960Number Of Labs/clbs4548
Total Ram Bits4520488Number Of I /o758
Voltage - Supply1.15 V ~ 1.25 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1020-FBGA
Family NameStratix IINumber Of Logic Blocks/elements90960
# I/os (max)758Frequency (max)711.24MHz
Process Technology90nm (CMOS)Operating Supply Voltage (typ)1.2V
Logic Cells90960Ram Bits4520488
Operating Supply Voltage (min)1.15VOperating Supply Voltage (max)1.25V
Operating Temp Range-40C to 100COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count1020
Package TypeFC-FBGALead Free Status / RoHS StatusLead free / RoHS Compliant
Number Of Gates-Other names544-1920
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Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial
interfacing ability.
Figure 2–45. Stratix II Device Fast PLL
Clock
Switchover
Circuitry (4)
Global or
regional clock (1)
4
Clock
Input
Global or
regional clock (1)
Shaded Portions of the
PLL are Reconfigurable
Notes to
Figure
2–45:
(1)
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2)
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3)
This signal is a differential I/O SERDES control signal.
(4)
Stratix II fast PLLs only support manual clock switchover.
(5)
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
f
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on enhanced and fast PLLs. See
Differential I/O with DPA Support” on page 2–96
on high-speed differential I/O support.
I/O Structure
The Stratix II IOEs provide many features, including:
Altera Corporation
May 2007
Figure 2–45
shows a diagram of the fast PLL.
Notes
(1), (2),
(3)
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
Charge
Loop
÷n
PFD
VCO
Pump
Filter
÷m
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip parallel termination
On-chip termination for differential standards
Programmable pull-up during configuration
Stratix II Architecture
Post-Scale
Counters
÷c0
(5)
8
÷k
÷c1
4
÷c2
4
8
÷c3
8
“High-Speed
for more information
Stratix II Device Handbook, Volume 1
diffioclk0
(2)
load_en0
(3)
(3)
load_en1
diffioclk1
(2)
Global clocks
Regional clocks
to DPA block
2–69