MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 101

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

21.2
Each of the PLLs listed above is provided with power through independent power supply pins
(AV
level should always be equivalent to V
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of 783 FC-PBGA the footprint, without the inductance of vias.
Figure 61
The AV
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
Figure
AV
near the AV
capacitor, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from
AV
frequency. All traces should be kept short, wide, and direct.
Freescale Semiconductor
DD
DD
DD
DD
_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be
_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
pins. By providing independent filters to each PLL the opportunity to cause noise injection from
_PLAT, AV
62. For maximum effectiveness, the filter circuit is placed as closely as possible to the
DD
PLL Power Supply Filtering
shows the PLL power supply filter circuit.
_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability
DD
_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by the 1-µF
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
DD
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
SV
V
DD
_CORE, AV
DD
Figure 61. MPC8533E PLL Power Supply Filter Circuit
Figure 62. SerDes PLL Power Supply Filter Circuit
1.0 Ω
10 Ω
DD
_PCI, AV
DD
2.2 µF
, and preferably these voltages will be derived directly from V
2.2 µF
DD
1
GND
_LBIU, and AV
GND
Low ESL Surface Mount Capacitors
2.2 µF
2.2 µF
1
DD
AV
0.003 µF
DD
_SRDS, respectively). The AV
DD
pin being supplied to minimize
Figure
AV
DD
_SRDS
61, one to each of the
System Design Information
DD
DD
DD
101