MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 45

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD, and LALE
Output hold from local bus clock (except LAD/LDP and
LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from BV
5. Input timings are measured at the pin.
6. The value of t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
for clock one (1). Also, t
to the output (O) going invalid (X) or output hold time.
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which proceeds LCLK
by t
complementary signals at BV
in question for 3.3-V signaling levels.
through the component pin is less than or equal to the leakage current specification.
LBKHKT
.
(first two letters of functional block)(reference)(state)(signal)(state)
LBOTOT
Table 43. Local Bus General Timing Parameters—PLL Bypassed (continued)
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
is the measurement of the minimum time between the negation of LALE and any change in LAD.
LBKHOX
DD
symbolizes local bus timing (LB) for the t
/2.
DD
/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BV
Symbol
t
t
t
t
t
t
LBKLOV2
LBKLOV3
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
LBK
LBK
clock reference (K) goes high (H), in this case
clock reference (K) to go high (H), with respect
Min
–4.1
–4.1
—
—
—
—
LBIXKH1
Max
1.6
1.6
1.4
1.4
—
—
symbolizes local bus
Unit
ns
ns
ns
ns
ns
ns
DD
of the signal
Local Bus
Notes
for
4
4
4
4
7
7
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