MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 25

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.3
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this
section.
8.3.1
The basis for the AC specifications for the eTSEC FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performance and are described in a source-synchronous fashion like
FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver.
A summary of the FIFO AC specifications appears in
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
TX_CLK, GTX_CLK clock period
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN
hold time
Note:
1. Data valid t
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
(Min setup = Cycle time – Max hold).
FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
FIFO AC Specifications
FITDV
Parameter/Condition
Parameter/Condition
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
to GTX_CLK Min setup time is a function of clock period and max hold time.
Table 23. FIFO Mode Transmit AC Timing Specification
Table 24. FIFO Mode Receive AC Timing Specification
t
FIRH
Symbol
Symbol
t
t
t
FITDX
t
t
t
t
FITH
FITR
t
FITJ
FITF
FIRJ
FIR
FIT
/t
FIRH
Table 23
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
Min
0.5
45
45
—
—
—
—
—
—
and
Table
Typ
Typ
8.0
8.0
50
50
—
—
—
—
—
24.
Max
0.75
0.75
Max
250
250
3.0
55
55
—
—
Unit
Unit
ns
ps
ns
ns
ns
ns
ps
%
%
Notes
Notes
—
—
—
—
—
—
—
—
1
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