MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 66

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

High-Speed Serial Interfaces (HSSI)
16.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 52
66
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge
rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should
not exceed 20% of the slowest edge rate. See
SDn_REF_CLK
SDn_REF_CLK
V
V
IH
IL
= +200 mV
= –200 mV
describes some AC parameters common to SGMII, and PCI Express protocols.
AC Requirements for SerDes Reference Clocks
minus
0.0 V
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
Figure 49. Differential Measurement Points for Rise and Fall Time
Table 52. SerDes Reference Clock Common AC Parameters
Rise Edge Rage
Figure
Figure
50.
49.
Rise-Fall Matching
Rise Edge Rate
Fall Edge Rate
Symbol
V
V
IH
IL
Fall Edge Rate
+200
Min
1.0
1.0
—
—
–200
Max
4.0
4.0
20
—
Freescale Semiconductor
Unit
V/ns
V/ns
mV
mV
%
Notes
2, 3
2, 3
1, 4
2
2