MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 31

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.5.1
Table 29
Figure 15
8.5.2
Table 30
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
GTX_CLK clock period
GTX_CLK to TCG[9:0] delay time
GTX_CLK rise (20%–80%)
GTX_CLK fall time (80%–20%)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. Data valid t
PMA_RX_CLK[0:1] clock period
PMA_RX_CLK[0:1] skew
inputs and t
transmit timing (TT) with respect to the time from t
state (V) or setup time. Also, t
high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of t
letter: R (rise) or F (fall).
delay).
TTX
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
provides the TBI transmit AC timing specifications.
provides the TBI receive AC timing specifications.
shows the TBI transmit AC timing diagram.
TTKHDV
TBI Transmit AC Timing Specifications
TBI Receive AC Timing Specifications
Parameter/Condition
Parameter/Condition
(first two letters of functional block)(reference)(state)(signal)(state)
GTX_CLK
TCG[9:0]
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time – Max
TTKHDX
Table 29. TBI Transmit AC Timing Specifications
Table 30. TBI Receive AC Timing Specifications
Figure 15. TBI Transmit AC Timing Diagram
t
TTXH
symbolizes the TBI transmit timing (TT) with respect to the time from t
t
TTKHDV
t
TTX
TTX
Symbol
Symbol
t
TTKHDX
t
(K) going high (H) until the referenced data signals (D) reach the valid
SKTRX
t
t
t
t
TTXR
TTXF
GTX
TRX
1
1
t
TTXF
(first two letters of functional block)(signal)(state )(reference)(state)
for outputs. For example, t
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
Min
0.2
7.5
—
—
—
—
t
TTKHDX
t
TTXR
16.0
Typ
Typ
8.0
—
—
—
—
TTKHDV
Max
Max
5.0
1.0
1.0
8.5
—
—
symbolizes the TBI
Unit
Unit
ns
ns
ns
ns
ns
ns
TTX
(K) going
Notes
Notes
—
—
—
—
—
2
for
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