MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 36

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.5.5.2
Table 34
Figure 20
Figure 21
36
At recommended operating conditions with L/TV
REF_CLK clock period
REF_CLK duty cycle
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
Fall time REF_CLK (80%–20%)
RXD[1:0], CRS_DV, RX_ER setup time to
REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
rising edge
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
shows the RMII receive AC timing specifications.
provides the AC test load for eTSEC.
shows the RMII receive AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter/Condition
RMII Receive AC Timing Specifications
REF_CLK
RXD[1:0]
CRS_DV
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
RX_ER
Output
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Table 34. RMII Receive AC Timing Specifications
Figure 21. RMII Receive AC Timing Diagram
t
RMRH
t
RMRDV
DD
MRX
Figure 20. eTSEC AC Test Load
of 3.3 V ± 5%.or 2.5 V ± 5%.
t
RMR
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRDXKL
Z
0
= 50 Ω
Symbol
t
t
t
t
RMRDX
t
RMRDV
t
RMRH
RMRR
symbolizes MII receive timing (GR) with respect to the time data input
t
RMRF
RMRJ
Valid Data
RMR
1
t
RMRF
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
15.0
Min
1.0
1.0
4.0
2.0
35
—
R
L
t
RMRDX
t
= 50 Ω
RMRR
20.0
Typ
50
—
—
—
—
—
LV
DD
MRDVKH
/2
Max
25.0
250
2.0
2.0
65
—
—
MRX
Freescale Semiconductor
symbolizes MII receive
clock reference (K)
Unit
ns
ps
ns
ns
ns
ns
%
Notes
—
—
—
—
—
—
—
for