MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 60

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV p-p.
16.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for PCI Express1 PCI Express2. SD2_REF_CLK and SD2_REF_CLK for the PCI
Express3. The following sections describe the SerDes reference clock requirements and some application
information.
16.2.1
Figure 41
60
OD
•
•
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
A Volts
B Volts
The supply voltage requirements for XV
SerDes reference clock receiver reference circuit structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
— The external reference clock driver must be able to drive this termination.
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
shown in
50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
SerDes Reference Clock Receiver Characteristics
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 40. Differential Voltage Definitions for Transmitter or Receiver
Figure
SDn_TX or
SDn_RX
SDn_TX or
SDn_RX
41. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
Differential Peak-Peak Voltage, V
DIFFp
Differential Swing, V
Differential Peak Voltage, V
) is 500 mV. The peak-to-peak differential voltage (V
DD_SRDS2
OD
is 500 mV in one phase and –500 mV in the other
are specified in
ID
or V
DIFFpp
OD
DIFFp
= 2*V
= A – B
= |A – B|
DIFFp
Table 1
(not shown)
and
Freescale Semiconductor
V
cm
Table
= (A + B) / 2
2.
DIFFp-p
)