MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 89

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB
frequency must equal the DDR data rate.
19.3
Table 61
ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in
19.4
For specifications on the PCI_CLK, refer to the PCI 2.2 Local Bus Specifications.
The use of PCI_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this
range then use of PCI_CLK is required as a separate PCI clock source, asynchronous with respect to
SYSCLK.
Freescale Semiconductor
LBCTL, LALE, LGPL2
Binary Value of
LA[28:31] Signals
Binary Value of
Signals
describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
000
001
010
011
e500 Core PLL Ratio
PCI Clocks
0000
0001
0010
0011
0100
0101
0110
0111
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
e500 core:CCB Clock Ratio
CCB:SYSCLK Ratio
Table 61. e500 Core to CCB Clock Ratio
Reserved
Reserved
Reserved
Reserved
Reserved
4:1
3:2
16:1
3:1
4:1
5:1
6:1
Table 60. CCB Clock Ratio
LBCTL, LALE, LGPL2
Binary Value of
LA[28:31] Signals
Binary Value of
Signals
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
e500 core:CCB Clock Ratio
CCB:SYSCLK Ratio
Reserved
Reserved
Reserved
Reserved
2:1
5:2
3:1
7:2
10:1
12:1
8:1
9:1
Table
Clocking
61.
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