MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 21

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 4
Freescale Semiconductor
At recommended operating conditions.
MDQS postamble
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
7. Maximum DDR1 frequency is 400 MHz.
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
outputs (A) are setup (S) or output valid time. Also, t
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock
adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been
set to the same adjustment value. See the MPC8533E PowerQUICC III Integrated Communications Processor Reference
Manual, for a description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
For the ADDR/CMD setup and hold specifications in
assumed that the clock control register is set to adjust the memory clocks by
½ applied cycle.
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
follows the symbol conventions described in note 1. For example, t
Table 18. DDR SDRAM Output AC Timing Specifications (continued)
MCK[n]
MCK[n]
MDQS
MDQS
Figure 4. Timing Diagram for t
Symbol
t
DDKHME
MCK
t
DDKHMH
DDKLDX
t
DDKHMH
1
memory clock reference (K) goes from the high (H) state until
t
NOTE
MCK
(min)
symbolizes DDR timing (DD) for the time t
(max)
0.4 x tMCK
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. Output hold time can be read as DDR timing
= –0.6 ns
Min
= 0.6 ns
DDKHMH
Table
DDKHMH
0.6 x tMCK
18, it is
Max
DDKHMH
describes the DDR timing
can be modified through
DDKHMP
DDR and DDR2 SDRAM
MCK
Unit
ns
memory clock
follows the
DDKHMH
Notes
for
6
21
).