MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet
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MPC8533E PowerQUICC™ III Integrated Host Processor Family Reference Manual Supports MPC8533E MPC8533 MPC8533ERM Rev. 1 10/2007 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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Reset, Clocking, and Initialization Part II—e500 Core Complex and L2 Cache Part III—Memory, Security, and I/O Interfaces Programmable Interrupt Controller Enhanced Three-Speed Ethernet Controllers Part IV—Global Functions and Debug Debug Features and Watchpoint Facility Complete List of Configuration, Control, and ...
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I Part I—Overview 1 Overview 2 Memory Map 3 Signal Descriptions 4 Reset, Clocking, and Initialization II Part II—e500 Core Complex and L2 Cache 5 Core Complex Overview 6 Core Register Summary 7 L2 Look-Aside Cache/SRAM III Part III—Memory, Security, ...
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... Multifunction Printer Application ............................................................................. 1-23 1.4.3 Security Appliance..................................................................................................... 1-24 1.4.4 IP SAN Host Adapter ................................................................................................ 1-25 1.4.5 VoIP Aggregation Application................................................................................... 1-26 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Contents About This Book Part I Overview Chapter 1 Overview ...
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... Signals Overview ............................................................................................................. 3-1 3.2 Configuration Signals Sampled at Reset ....................................................................... 3-15 3.3 Output Signal States During Reset ................................................................................ 3-16 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Chapter 2 Memory Map Chapter 3 Signal Descriptions Chapter 4 Reset, Clocking, and Initialization Page Number Freescale Semiconductor ...
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... PCI I/O Impedance ................................................................................................ 4-20 4.4.3.17 PCI Arbiter Configuration ..................................................................................... 4-20 4.4.3.18 Memory Debug Configuration .............................................................................. 4-20 4.4.3.19 DDR Debug Configuration.................................................................................... 4-20 4.4.3.20 General-Purpose POR Configuration .................................................................... 4-21 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number vii ...
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... Atomic Update Memory References ......................................................................... 5-27 5.10.2 Memory Access Ordering.......................................................................................... 5-27 5.10.3 Cache Control Instructions ........................................................................................ 5-27 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 viii Contents Title Part II e500 Core Complex and L2 Cache Chapter 5 Core Complex Overview Page Number Freescale Semiconductor ...
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... Timer Control Register (TCR)................................................................................... 6-14 6.6.2 Timer Status Register (TSR)...................................................................................... 6-15 6.6.3 Time Base Registers .................................................................................................. 6-16 6.6.4 Decrementer Register ................................................................................................ 6-16 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 6 Core Register Summary Page Number ix ...
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... MMU Assist Registers............................................................................................... 6-35 6.12.5.1 MAS Register 0 (MAS0) ....................................................................................... 6-35 6.12.5.2 MAS Register 1 (MAS1) ....................................................................................... 6-35 6.12.5.3 MAS Register 2 (MAS2) ....................................................................................... 6-36 6.12.5.4 MAS Register 3 (MAS3) ....................................................................................... 6-37 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... L2 Memory-Mapped SRAM Registers ................................................................. 7-15 7.3.1.3.1 L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn) ........ 7-16 7.3.1.3.2 L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1 (L2SRBAREAn)............................................................................................ 7-17 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 7 L2 Look-Aside Cache/SRAM Page Number ...
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... Introduction...................................................................................................................... 8-1 8.1.1 Overview...................................................................................................................... 8-2 8.1.2 Features........................................................................................................................ 8-2 8.2 Memory Map/Register Definition ................................................................................... 8-3 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xii Contents Title Part III Memory, Security, and I/O Interfaces Chapter 8 e500 Coherency Module Page Number Freescale Semiconductor ...
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... DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-20 9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-23 9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-25 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 9 DDR Memory Controller Page Number ...
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... DDR Data Beat Ordering........................................................................................... 9-64 9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-64 9.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-65 9.5.12 Error Management ..................................................................................................... 9-67 9.6 Initialization/Application Information ........................................................................... 9-68 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xiv Contents Title Page Number Freescale Semiconductor ...
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... Global Timer Base Count Registers (GTBCRn).................................................. 10-23 10.3.2.4 Global Timer Vector/Priority Registers (GTVPRn)............................................. 10-24 10.3.2.5 Global Timer Destination Registers (GTDRn) .................................................... 10-25 10.3.2.6 Timer Control Register (TCR)............................................................................. 10-25 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 10 Programmable Interrupt Controller Page Number xv ...
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... Flow of Interrupt Control......................................................................................... 10-47 10.4.1.1 Interrupt Source Priority ...................................................................................... 10-49 10.4.1.2 Processor Current Task Priority........................................................................... 10-49 10.4.1.3 Interrupt Acknowledge ........................................................................................ 10-49 10.4.2 Nesting of Interrupts ................................................................................................ 10-50 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xvi Contents Title Page Number Freescale Semiconductor ...
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... Transaction Monitoring—Implementation Details.......................................... 11-14 11.4.1.5.2 Control Transfer—Implementation Details ..................................................... 11-14 11.4.1.6 Address Compare—Implementation Details ....................................................... 11-15 11.4.2 Arbitration Procedure .............................................................................................. 11-15 11.4.2.1 Arbitration Control .............................................................................................. 11-15 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter Interfaces Page Number xvii ...
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... Kasumi Execution Unit (KEU).............................................................................. 12-8 12.1.3 Crypto-Channels ........................................................................................................ 12-8 12.1.4 Controller ................................................................................................................... 12-9 12.1.4.1 Channel-Controlled Access ................................................................................. 12-10 12.1.4.2 Host-Controlled Access ....................................................................................... 12-10 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xviii Contents Title Chapter 12 Security Engine (SEC) 2.1 Page Number Freescale Semiconductor ...
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... ARC Four Execution Unit (AFEU) ......................................................................... 12-41 12.4.3.1 AFEU Mode Register (AFEUMR)...................................................................... 12-42 12.4.3.2 Host-Provided Context via Prevent Permute....................................................... 12-42 12.4.3.2.1 Dump Context.................................................................................................. 12-42 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xix ...
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... AESU Key Size Register (AESUKSR) ............................................................... 12-69 12.4.6.3 AESU Data Size Register (AESUDSR) .............................................................. 12-69 12.4.6.4 AESU Reset Control Register (AESURCR) ....................................................... 12-70 12.4.6.5 AESU Status Register (AESUSR)....................................................................... 12-71 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... Channel Interrupts.................................................................................................. 12-103 12.5.2.1 Channel Done Interrupt ..................................................................................... 12-103 12.5.2.2 Channel Error Interrupt...................................................................................... 12-103 12.5.2.3 Channel Reset .................................................................................................... 12-103 12.6 Security Controller..................................................................................................... 12-104 12.6.1 Assignment of EUs to Channels ............................................................................ 12-104 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxi ...
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... Line Control Registers (ULCR0, ULCR1).......................................................... 13-12 13.3.1.8 Modem Control Registers (UMCR0, UMCR1)................................................... 13-14 13.3.1.9 Line Status Registers (ULSR0, ULSR1) ............................................................. 13-15 13.3.1.10 Modem Status Registers (UMSR0, UMSR1) ...................................................... 13-16 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxii Contents Title Chapter 13 DUART Page Number Freescale Semiconductor ...
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... Option Registers (ORn)—UPM Mode ............................................................ 14-15 14.3.1.2.4 Option Registers (ORn)—SDRAM Mode ...................................................... 14-16 14.3.1.3 UPM Memory Address Register (MAR)............................................................. 14-17 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 14 Local Bus Controller Page Number ...
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... Intel PC133 and JEDEC-Standard SDRAM Interface Commands ..................... 14-49 14.4.3.4 Page Hit Checking ............................................................................................... 14-50 14.4.3.5 Page Management................................................................................................ 14-50 14.4.3.6 SDRAM Address Multiplexing ........................................................................... 14-50 14.4.3.7 SDRAM Device-Specific Parameters.................................................................. 14-51 14.4.3.7.1 Precharge-to-Activate Interval......................................................................... 14-52 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxiv Contents Title Page Number Freescale Semiconductor ...
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... Multiplexed Address/Data Bus and Non-Multiplexed Address Signals ............. 14-79 14.5.1.2 Peripheral Hierarchy on the Local Bus................................................................ 14-80 14.5.1.3 Peripheral Hierarchy on the Local Bus for Very High Bus Speeds..................... 14-80 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxv ...
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... Overview........................................................................................................................ 15-1 15.2 Features .......................................................................................................................... 15-2 15.3 Modes of Operation ....................................................................................................... 15-4 15.4 External Signals Description ......................................................................................... 15-6 15.4.1 Detailed Signal Descriptions ..................................................................................... 15-8 15.5 Memory Map/Register Definition ............................................................................... 15-12 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxvi Contents Title Chapter 15 Page Number Freescale Semiconductor ...
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... Receive Descriptor Base Address High Register (RBASEH)......................... 15-63 15.5.3.3.13 Receive Descriptor Base Address Registers (RBASE0–RBASE7) ................ 15-63 15.5.3.4 MAC Functionality.............................................................................................. 15-64 15.5.3.4.1 Configuring the MAC ..................................................................................... 15-64 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxvii ...
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... Receive Control Frame Packet Counter (RXCF) ............................................ 15-85 15.5.3.6.14 Receive Pause Frame Packet Counter (RXPF)................................................ 15-86 15.5.3.6.15 Receive Unknown Opcode Packet Counter (RXUO)...................................... 15-86 15.5.3.6.16 Receive Alignment Error Counter (RALN) .................................................... 15-87 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxviii Contents Title Page Number Freescale Semiconductor ...
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... DMA Attribute Registers................................................................................... 15-110 15.5.3.9.1 Attribute Register (ATTR)............................................................................. 15-110 15.5.3.9.2 Attribute Extract Length and Extract Index Register (ATTRELI) ................15-111 15.5.3.10 Lossless Flow Control Configuration Registers ................................................ 15-112 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxix ...
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... FIFO Interface Signal Summary........................................................................ 15-140 15.6.3 Gigabit Ethernet Controller Channel Operation .................................................... 15-141 15.6.3.1 Initialization Sequence....................................................................................... 15-141 15.6.3.1.1 Hardware Controlled Initialization................................................................ 15-141 15.6.3.1.2 User Initialization .......................................................................................... 15-141 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxx Contents Title Page Number Freescale Semiconductor ...
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... Lossless Flow Control ........................................................................................... 15-170 15.6.6.1 Back Pressure Determination via Free Buffers.................................................. 15-170 15.6.6.2 Software Use of Hardware-Initiated Back Pressure .......................................... 15-172 15.6.6.2.1 Initialization................................................................................................... 15-172 15.6.6.2.2 Operation ....................................................................................................... 15-172 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxi ...
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... Byte Count Registers (BCRn) ............................................................................. 16-19 16.3.1.9 Next Link Descriptor Address Registers (NLNDARn and ENLNDARn) ....................................................................... 16-19 16.3.1.10 Current List Descriptor Address Registers (CLSDARn and ECLSDARn)......................................................................... 16-21 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxii Contents Title Chapter 16 DMA Controller Page Number Freescale Semiconductor ...
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... DMA to Ethernet ................................................................................................. 16-40 16.5.1.3 DMA to Configuration, Control, and Status Registers........................................ 16-40 2 16.5.1.4 DMA to I 16.5.1.5 DMA to DUART ................................................................................................. 16-41 17.1 Introduction.................................................................................................................... 17-2 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title C ......................................................................................................... 16-40 Chapter 17 PCI Bus Interface Page Number xxxiii ...
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... PCI Error Data Low Capture Register (ERR_DL) .......................................... 17-29 17.3.1.4.8 PCI Error Data High Capture Register (ERR_DH)......................................... 17-29 17.3.1.4.9 PCI Gasket Timer Register (GAS_TIMR) ...................................................... 17-29 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxiv Contents Title Page Number Freescale Semiconductor ...
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... Bus Driving and Turnaround ............................................................................... 17-49 17.4.2.7 PCI Bus Transactions........................................................................................... 17-50 17.4.2.7.1 PCI Read Transactions .................................................................................... 17-50 17.4.2.7.2 PCI Write Transactions.................................................................................... 17-51 17.4.2.8 Transaction Termination ...................................................................................... 17-52 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxv ...
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... PCI Express Configuration Access Registers............................................................ 18-9 18.3.2.1 PCI Express Configuration Address Register (PEX_CONFIG_ADDR) .............. 18-9 18.3.2.2 PCI Express Configuration Data Register (PEX_CONFIG_DATA)................... 18-10 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxvi Contents Title Chapter 18 PCI Express Interface Controller Page Number Freescale Semiconductor ...
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... PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)............................ 18-38 18.3.6.7 PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)............................ 18-39 18.3.6.8 PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)............................ 18-40 18.3.7 PCI Express Configuration Space Access ............................................................... 18-42 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxvii ...
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... PCI Express Prefetchable Base Upper 32 Bits Register—0x28...................... 18-63 18.3.8.3.14 PCI Express Prefetchable Limit Upper 32 Bits Register—0x2C .................... 18-63 18.3.8.3.15 PCI Express I/O Base Upper 16 Bits Register—0x30 .................................... 18-63 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxviii Contents Title Page Number Freescale Semiconductor ...
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... PCI Express Header Log Register—0x11C–0x12B ............................................ 18-87 18.3.10.9 PCI Express Root Error Command Register—0x12C......................................... 18-88 18.3.10.10 PCI Express Root Error Status Register—0x130 ................................................ 18-88 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxix ...
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... Power Management ............................................................................................... 18-108 18.4.4.1 L2/L3 Ready Link State..................................................................................... 18-108 18.4.5 Hot Reset................................................................................................................ 18-109 18.5 Initialization/Application Information ....................................................................... 18-109 18.5.1 Boot Mode and Inbound Configuration Transactions ........................................... 18-109 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... DDR Clock Disable Register (DDRCLKDR) ..................................................... 19-22 19.4.1.23 Clock Out Control Register (CLKOCR) ............................................................. 19-23 19.4.1.24 SerDes 1 Control Register 1 (SRDS1CR1) ......................................................... 19-24 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Part IV Global Functions and Debug Chapter 19 Global Utilities ...
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... Functional Description................................................................................................. 20-11 20.4.1 Performance Monitor Interrupt................................................................................ 20-11 20.4.2 Event Counting ........................................................................................................ 20-12 20.4.3 Threshold Events ..................................................................................................... 20-12 20.4.4 Chaining................................................................................................................... 20-13 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xlii Contents Title Chapter 20 Device Performance Monitor Page Number Freescale Semiconductor ...
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... Trace Buffer Access Data Register (TBADR)..................................................... 21-22 21.3.3 Context ID Registers................................................................................................ 21-23 21.3.3.1 Programmed Context ID Register (PCIDR) ........................................................ 21-23 21.3.3.2 Current Context ID Register (CCIDR) ................................................................ 21-24 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 21 Page Number xliii ...
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... Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 21-28 21.5 Initialization ................................................................................................................. 21-31 A.1 Changes From Revision 0 to Revision 1 ........................................................................ A-1 Complete List of Configuration, Control, and Status Registers MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xliv Contents Title Appendix A Revision History Appendix B Glossary Index Page Number Freescale Semiconductor ...
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... Core Programming Model............................................................................................ 5-17 5-8 MMU Structure ..................................................................................................................... 5-23 5-9 Effective-to-Real Address Translation Flow......................................................................... 5-24 5-10 Effective-to-Real Address Translation Flow (e500v2) ......................................................... 5-25 6-1 Core Register Model ............................................................................................................... 6-2 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Figures Page Number xlv ...
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... MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-32 6-40 MMU Configuration Register (MMUCFG) ......................................................................... 6-32 6-41 TLB Configuration Register 0 (TLB0CFG) ......................................................................... 6-33 6-42 TLB Configuration Register 1 (TLB1CFG) ......................................................................... 6-34 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xlvi Figures Title Page Number Freescale Semiconductor ...
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... L2 Error Injection Mask Low Register (L2ERRINJLO) ...................................................... 7-18 7-15 L2 Error Injection Mask Control Register (L2ERRINJCTL) ............................................... 7-19 7-16 L2 Error Capture Data High Register (L2CAPTDATAHI)................................................... 7-20 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number xlvii ...
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... DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-31 9-17 DDR Initialization Extended Address Configuration Register (DDR_INIT_EXT_ADDR).............................................................................................. 9-31 9-18 DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-32 9-19 DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-32 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xlviii Figures Title Page Number Freescale Semiconductor ...
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... IPI Vector/Priority Register (IPIVPRn) .............................................................................. 10-21 10-10 Spurious Vector Register (SVR) ......................................................................................... 10-22 10-11 Timer Frequency Reporting Register (TFRR) .................................................................... 10-22 10-12 Global Timer Current Count Registers (GTCCRn)............................................................. 10-23 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number xlix ...
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... I C Block Diagram................................................................................................................ 11 Address Register (I2CADR)........................................................................................... 11 Frequency Divider Register (I2CFDR) .......................................................................... 11 Control Register (I2CCR)............................................................................................... 11 Status Register (I2CSR) ................................................................................................. 11-9 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...
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... MDEU Key Size Register ................................................................................................... 12-54 12-32 MDEU Data Size Register .................................................................................................. 12-55 12-33 MDEU Reset Control Register ........................................................................................... 12-55 12-34 MDEU Status Register........................................................................................................ 12-56 12-35 MDEU Interrupt Status Register ......................................................................................... 12-57 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number li ...
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... Crypto-Channel Configuration Register (CCCR)............................................................... 12-92 12-73 Header Dword Writeback Format ....................................................................................... 12-94 12-74 Crypto-Channel Pointer Status Register ............................................................................. 12-95 12-75 Crypto-Channel Current Descriptor Pointer Register ....................................................... 12-100 12-76 Fetch FIFO ........................................................................................................................ 12-101 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lii Figures Title Page Number Freescale Semiconductor ...
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... Transfer Error Status Register (LTESR) ............................................................................. 14-24 14-14 Transfer Error Check Disable Register (LTEDR) ............................................................... 14-25 14-15 Transfer Error Interrupt Enable Register (LTEIR).............................................................. 14-26 14-16 Transfer Error Attributes Register (LTEATR) .................................................................... 14-27 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number liii ...
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... SDRAM Three-Beat Write, Page Closed............................................................................ 14-56 14-48 SDRAM Read-After-Read Pipelined, Page Hit 3..................................................... 14-56 14-49 SDRAM Write-After-Write Pipelined, Page Hit................................................................. 14-56 14-50 SDRAM Read-After-Write Pipelined, Page Hit ................................................................. 14-57 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 liv Figures Title Page Number Freescale Semiconductor ...
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... Synchronous Single Read from MSC8102 DSI................................................................ 14-109 14-89 Synchronous Burst Write to MSC8102 DSI ..................................................................... 14-110 14-90 Synchronous Burst Read from MSC8102 DSI ..................................................................14-111 15-1 eTSEC Block Diagram.......................................................................................................... 15-2 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lv ...
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... Half-Duplex Register Definition......................................................................................... 15-71 15-40 Maximum Frame Length Register Definition..................................................................... 15-72 15-41 MII Management Configuration Register Definition ......................................................... 15-72 15-42 MIIMCOM Register Definition .......................................................................................... 15-73 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lvi Figures Title Page Number Freescale Semiconductor ...
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... Transmit Deferral Packet Counter Register Definition....................................................... 15-94 15-82 Transmit Excessive Deferral Packet Counter Register Definition...................................... 15-94 15-83 Transmit Single Collision Packet Counter Register Definition .......................................... 15-95 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lvii ...
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... Connection............................................................................................... 15-130 15-121 eTSEC-TBI Connection .................................................................................................... 15-131 15-122 eTSEC-RTBI Connection ................................................................................................. 15-132 15-123 eTSEC-FIFO (8-Bit) Connection...................................................................................... 15-139 15-124 8-Bit GMII-Style Packet FIFO Timing............................................................................. 15-139 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lviii Figures Title Page Number Freescale Semiconductor ...
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... External Control Interface Timing ...................................................................................... 16-31 16-24 Stride Size and Stride Distance ........................................................................................... 16-33 16-25 DMA Transaction Flow with DMA Descriptors ................................................................ 16-36 16-26 List Descriptor Format ........................................................................................................ 16-37 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lix ...
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... Memory Base Address Register .............................................................................. 17-37 17-37 64-Bit Low Memory Base Address Register ...................................................................... 17-37 17-38 64-Bit High Memory Base Address Register ..................................................................... 17-38 17-39 PCI Subsystem Vendor ID Register .................................................................................... 17-38 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...
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... IP Block Revision Register 1 .............................................................................................. 18-18 18-12 IP Block Revision Register 2 .............................................................................................. 18-19 18-13 RC Outbound Transaction Flow ......................................................................................... 18-20 18-14 PCI Express Outbound Translation Address Registers (PEXOTARn) ............................... 18-20 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxi ...
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... PCI Express Bus Cache Line Size Register ........................................................................ 18-48 18-44 PCI Express Bus Latency Timer Register........................................................................... 18-49 18-45 PCI Express Bus Latency Timer Register........................................................................... 18-49 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxii Figures Title Page Number Freescale Semiconductor ...
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... PCI Express Capability ID Register.................................................................................... 18-70 18-84 PCI Express Capabilities Register ...................................................................................... 18-70 18-85 PCI Express Device Capabilities Register .......................................................................... 18-71 18-86 PCI Express Device Control Register ................................................................................. 18-71 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxiii ...
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... Address Invariant Byte Ordering—4 bytes Outbound........................................................ 18-99 18-126 Address Invariant Byte Ordering—4 bytes Inbound .......................................................... 18-99 18-127 Address Invariant Byte Ordering—8 bytes Outbound...................................................... 18-100 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxiv Figures Title Page Number Freescale Semiconductor ...
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... Performance Monitor Counter Register (PMC1–PMC9) ................................................... 20-11 20-9 Duration Threshold Event Sequence Timing Diagram ....................................................... 20-13 20-10 Burst Size, Distance, Granularity, and Burstiness Counting............................................... 20-14 20-11 Burstiness Counting Timing Diagram ................................................................................ 20-16 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxv ...
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... Coherency Module Dispatch (CMD) Trace Buffer Entry .......................................... 21-28 21-21 DDR Trace Buffer Entry ..................................................................................................... 21-29 21-22 PCI Trace Buffer Entry ....................................................................................................... 21-30 21-23 PCI Express Trace Buffer Entry.......................................................................................... 21-30 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxvi Figures Title Page Number Freescale Semiconductor ...
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... PCI Clock Select ................................................................................................................... 4-19 4-23 PCI Speed Configuration ...................................................................................................... 4-19 4-24 PCI I/O Impedance................................................................................................................ 4-20 4-25 PCI Arbiter Configuration .................................................................................................... 4-20 4-26 Memory Debug Configuration.............................................................................................. 4-20 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Tables Page Number lxvii ...
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... MAS0 Field Descriptions—MMU Read/Write and Replacement Control .......................... 6-35 6-29 MAS1 Field Descriptions—Descriptor Context and Configuration Control........................ 6-36 6-30 MAS2 Field Descriptions—EPN and Page Attributes ......................................................... 6-36 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxviii Tables Title Page Number Freescale Semiconductor ...
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... L2ERRCTL Field Descriptions ............................................................................................ 7-25 7-23 Fastest Read Timing—Hit in L2 ........................................................................................... 7-27 7-24 PLRU Bit Update Algorithm ................................................................................................ 7-32 7-25 PLRU-Based Victim Selection Mechanism .......................................................................... 7-33 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxix ...
Page 70
... DDR_INIT_EXT_ADDR Field Descriptions....................................................................... 9-31 9-23 DDR_IP_REV1 Field Descriptions ...................................................................................... 9-32 9-24 DDR_IP_REV2 Field Descriptions ...................................................................................... 9-32 9-25 DATA_ERR_INJECT_HI Field Descriptions....................................................................... 9-33 9-26 DATA_ERR_INJECT_LO Field Descriptions ..................................................................... 9-33 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxx Tables Title Page Number Freescale Semiconductor ...
Page 71
... BRR1 Field Descriptions .................................................................................................... 10-18 10-8 BRR2 Field Descriptions .................................................................................................... 10-18 10-9 FRR Field Descriptions....................................................................................................... 10-19 10-10 GCR Field Descriptions ...................................................................................................... 10-19 10-11 VIR Field Descriptions ....................................................................................................... 10-20 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxi ...
Page 72
... CTPR Field Descriptions .................................................................................................... 10-45 10-49 WHOAMI Field Descriptions ............................................................................................. 10-46 10-50 IACK Field Descriptions .................................................................................................... 10-47 10-51 EOI Field Descriptions........................................................................................................ 10-47 10-52 PCI Express INTx/IRQn Sharing........................................................................................ 10-51 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxii Tables Title Page Number Freescale Semiconductor ...
Page 73
... Mode Register —HMAC Generated Across a Sequence of Descriptors............................ 12-54 12-30 MDEU Reset Control Register Field Descriptions ............................................................. 12-55 12-31 MDEU Status Register Field Descriptions ......................................................................... 12-56 12-32 MDEU Interrupt Status Register Field Descriptions .......................................................... 12-57 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxiii ...
Page 74
... UDLB Field Descriptions ..................................................................................................... 13-8 13-8 Baud Rate Examples ............................................................................................................. 13-8 13-9 UIER Field Descriptions ....................................................................................................... 13-9 13-10 UIIR Field Descriptions ...................................................................................................... 13-10 13-11 UIIR IID Bits Summary...................................................................................................... 13-10 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxiv Tables Title Page Number Freescale Semiconductor ...
Page 75
... Boot Bank Field Values After Reset ................................................................................... 14-47 14-26 SDRAM Interface Commands ............................................................................................ 14-49 14-27 UPM Routines Start Addresses........................................................................................... 14-60 14-28 RAM Word Field Descriptions ........................................................................................... 14-65 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxv ...
Page 76
... TR03WT Field Descriptions ............................................................................................... 15-45 15-21 TR47WT Field Descriptions ............................................................................................... 15-46 15-22 TBDBPH Field Descriptions .............................................................................................. 15-46 15-23 TBPTRn Field Descriptions ................................................................................................ 15-47 15-24 TBASEH Field Descriptions............................................................................................... 15-47 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxvi Tables Title Page Number Freescale Semiconductor ...
Page 77
... TRMGV Field Descriptions................................................................................................ 15-82 15-62 RBYT Field Descriptions.................................................................................................... 15-83 15-63 RPKT Field Descriptions .................................................................................................... 15-83 15-64 RFCS Field Descriptions .................................................................................................... 15-84 15-65 RMCA Field Descriptions .................................................................................................. 15-84 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxvii ...
Page 78
... RREJ Field Descriptions ................................................................................................... 15-107 15-103 IGADDRn Field Descriptions........................................................................................... 15-108 15-104 GADDRn Field Descriptions ............................................................................................ 15-108 15-105 FIFOCFG Field Descriptions............................................................................................ 15-109 15-106 ATTR Field Descriptions ...................................................................................................15-111 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxviii Tables Title Page Number Freescale Semiconductor ...
Page 79
... Filer Table Example—TCP and UDP Port Filing............................................................. 15-167 15-146 Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 15-176 15-147 Receive Buffer Descriptor Field Descriptions .................................................................. 15-179 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxix ...
Page 80
... NLSDARn Field Descriptions ............................................................................................ 16-22 16-18 SSRn Field Descriptions ..................................................................................................... 16-23 16-19 DSRn Field Descriptions .................................................................................................... 16-23 16-20 DGSR Field Descriptions.................................................................................................... 16-24 16-21 Channel State Table............................................................................................................. 16-32 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxx Tables Title Page Number Freescale Semiconductor ...
Page 81
... Bit Setting for 64-Bit High Memory Base Address Register.............................................. 17-38 17-38 PCI Subsystem Vendor ID Register Field Description ....................................................... 17-38 17-39 PCI Subsystem ID Register Field Description.................................................................... 17-39 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxi ...
Page 82
... PCI Express Inbound Window Attributes Registers Field Descriptions............................. 18-27 18-23 PCI Express Error Detect Register Field Descriptions ....................................................... 18-30 18-24 PCI Express Error Interrupt Enable Register Field Descriptions ....................................... 18-32 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxii Tables Title Page Number Freescale Semiconductor ...
Page 83
... PEXCSRBAR Field Descriptions ....................................................................................... 18-57 18-56 PCI Express Primary Bus Number Register Field Description .......................................... 18-57 18-57 PCI Express Secondary Bus Number Register Field Description ...................................... 18-58 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxiii ...
Page 84
... PCI Express MSI Message Data Register Field Description.............................................. 18-80 18-96 PCI Express Advanced Error Reporting Capability ID Register Field Description.............................................................................................. 18-82 18-97 PCI Express Uncorrectable Error Status Register Field Description.................................. 18-82 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxiv Tables Title Page Number Freescale Semiconductor ...
Page 85
... GPPORCR Field Descriptions ............................................................................................ 19-11 19-11 GPIOCR Field Descriptions................................................................................................ 19-12 19-12 GPOUTDR Field Descriptions ........................................................................................... 19-12 19-13 GPINDR Field Descriptions ............................................................................................... 19-13 19-14 PMUXCR Field Descriptions ............................................................................................. 19-14 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxv ...
Page 86
... WMAR Field Descriptions ................................................................................................. 21-13 21-10 WMAMR Field Descriptions.............................................................................................. 21-14 21-11 WMTMR Field Descriptions .............................................................................................. 21-14 21-12 Transaction Types by Interface ........................................................................................... 21-15 21-13 WMSR Field Descriptions .................................................................................................. 21-16 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxvi Tables Title Page Number Freescale Semiconductor ...
Page 87
... PCI Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 010) ................................................................................................. 21-30 21-30 PCI Express Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 100 or 101 or 110)........................................................................... 21-30 B-1 Memory Map...........................................................................................................................B-1 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxvii ...
Page 88
... Table Number MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxviii Tables Title Page Number Freescale Semiconductor ...
Page 89
... Chapter 6, “Core Register Summary,” MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor provides a high-level description of features and functionality of the describes the device memory map. An overview of the local address lists all the external signals, cross-references for signals that ...
Page 90
... I 2.1,” describes the security controller of the MPC8533E. describes the (dual) universal asynchronous receiver/transmitters describes the local bus controller of the MPC8533E. The main 2 C) bus controllers of the MPC8533E controller to initialize describes the two enhanced Freescale Semiconductor ...
Page 91
... The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, by International Business Machines, Inc. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor describes the four-channel general-purpose DMA controller of the describes the PCI controller of the MPC8533E. Controller,” describes the PCI-Express implementation of the defines the global utilities of the MPC8533E ...
Page 92
... Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale processors. Additional literature is published as new processors become available. For a current list of documentation, refer to http://www.freescale.com. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xcii describes the functionality of the e500 Freescale Semiconductor ...
Page 93
... Indicates a read-only bit field in a memory-mapped register. R FIELDNAME W Indicates a write-only bit field in a memory-mapped register. Although these bits R can be written to as ones or zeros, they are always read as zeros. W FIELDNAME MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor xciii ...
Page 94
... Enhanced host port interface EPROM Erasable programmable read-only memory FCS Frame-check sequence GCI General circuit interface MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xciv Section 3.2, “Configuration Signals Sampled at Reset.” Table i. Acronyms and Abbreviated Terms Meaning Freescale Semiconductor ...
Page 95
... Nonmultiplexed serial interface No-op No operation OCeaN On-chip network OSI Open systems interconnection PCI Peripheral component interconnect bus PCMCIA Personal Computer Memory Card International Association PCS Physical coding sublayer MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Meaning xcv ...
Page 96
... Time-slot assigner TSEC Three-speed Ethernet controller Tx Transmit TxBD Transmit buffer descriptor UART Universal asynchronous receiver/transmitter UPM User-programmable machine UTP Unshielded twisted pair VA Virtual address ZBT Zero bus turnaround MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xcvi Meaning Freescale Semiconductor ...
Page 97
... Chapter 4, “Reset, Clocking, and Initialization,” sequence, power-on reset (POR) configuration, clocking, and initialization of the MPC8533E. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor provides a listing of all the external signals, cross-references for signals describes the hard and soft resets, power-on reset ...
Page 98
... Overview MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 I-2 Freescale Semiconductor ...
Page 99
... The MPC8533E is also available without a security engine configuration known as the MPC8533. All specifications other than those relating to security apply to the MPC8533 exactly as described in this document. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 2 C controllers, a four-channel 1-1 ...
Page 100
... Switch Fabric 32-bit PCI Bus Interface 4-Channel DMA Figure 1-1. MPC8533E Block Diagram Figure 1-1 shows the major functional e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache PCI Express dual x4 and Interfaces single x1 PCI 32-bit 66 MHz External Control Controller Freescale Semiconductor ...
Page 101
... Contiguous or discontiguous memory mapping — Chip-select interleaving support — Sleep mode support for self-refresh SDRAM MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor includes a comprehensive list of e500 core features. Section 1.3.2, “On-Chip Memory Unit” Overview ...
Page 102
... Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, and CCM modes – 128-, 192-, and 256-bit key lengths MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-4 m and F(p) modes and programmable field size Freescale Semiconductor ...
Page 103
... Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8, 16 bits) MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 2 C addressing mode Overview 2 ...
Page 104
... VRRP and HSRP support for seamless router fail-over – exact-match MAC addresses supported – Broadcast address (accept/reject) – Hash table match 512 multicast addresses MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-6 Section 1.3.13, for more information. Freescale Semiconductor ...
Page 105
... Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency • PCI Express interfaces — PCI Express 1.0a compatible — Supports dual x4 and single x1 links MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-7 ...
Page 106
... This device uses the e500 microprocessor core complex. The e500 core has an internal PLL that allows independent optimization of the operating frequencies. The core frequencies are derived from either the MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-8 Freescale Semiconductor ...
Page 107
... Pseudo-LRU replacement algorithm — Copy-back data cache • Dual-dispatch superscalar • Precise exception handling MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE NOTE Overview 1-9 ...
Page 108
... Book E instructions also executes the lower half of 64-bit SPE APU instructions. — Single-cycle integer add and subtract — Single-cycle logical operations — Single-cycle shift and rotate MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-10 Freescale Semiconductor ...
Page 109
... Floating-point data exception – Floating-point round exception – Performance monitor • Memory management unit (MMU) — Data L1 MMU – Four-entry, fully-associative TLB array for variable-sized pages MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-11 ...
Page 110
... Stashing of I/O data into the L2 array is supported, but can be limited to a 1-, 2-, or 4-way basis — SRAM operation is byte-accessible. — Data ECC on 64-bit boundaries (single-error correction, double-error detection) MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev virtual memory physical memory Freescale Semiconductor ...
Page 111
... I/O writes that correspond to a programmable address window or that use a special transaction type (stashing). In this way, DMA engines or I/O devices can force data into the cache. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-13 ...
Page 112
... MPC8533E interrupt controller to the IRQ_OUT signal. The IRQ_OUT signal from the interrupt controller is steered to an enable bit in the DDR controller which immediately causes main memory to enter self-refresh mode. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-14 Freescale Semiconductor ...
Page 113
... The version of the SEC used in the MPC8533E is specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and IEEE Std. 802.11i ™. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE Overview 1-15 ...
Page 114
... C) interfaces. The controller consists of a transmitter/receiver 2 C units support general broadcast mode, and on-chip Figure 1-2. The bus FIFO FIFO FIFO AESU AFEU KEU RNG FIFO FIFO FIFO FIFO 2 C bus is a two-wire, bidirectional 2 C devices such allows the Freescale Semiconductor ...
Page 115
... JEDEC–compliant SDRAM devices. An internal PLL (phase-locked loop) for bus clock generation ensures improved data setup margins for board designs. The SDRAM MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 2 C interface to access an external serial ROM ...
Page 116
... Bare IP packets, with an optional 32-bit CRC check sequence, can be transferred to the eTSEC directly. The eTSEC Tx and Rx FIFOs, TCP/IP acceleration functions, and DMA continue to be used in packet FIFO mode. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-18 Freescale Semiconductor ...
Page 117
... The interface is selectable at boot time to support either 32 or 64-bit addressing. The maximum supported packet payload size is 256 bytes. The physical layer supports dual x4 links and a single x1 link. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-19 ...
Page 118
... The local address map is 64 Gbytes. The MPC8533E can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-20 Freescale Semiconductor ...
Page 119
... ECM are coherent transactions; all others (across the on-chip fabric) are non-coherent. 1.4 Application Examples The MPC8533E is a very flexible device and can be configured to meet many system application needs. The following section provides block diagrams of various applications. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figure 1-3 Overview ...
Page 120
... Figure 1-4. Multifunction Router Application Enabled by local bus, PCI Express, MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-22 DDR/DDR-2 Flash SDRAM Local Bus DDR MPC8533E S/RGMII SEC PCIe ASIC/FPGA PCI, and Ethernet RGMII 5/9 Port GE Switch w/PHY 10/100/1000 Ethernet Network Interface Freescale Semiconductor ...
Page 121
... USB2.0 SATA S/RGMII 10/100/1000 Ethernet Network Interface Maintenance/Debug Port Figure 1-5. Multifunction Printer Application Enabled by Local Bus, PCI Express, MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor DDR/DDR-2 Flash SDRAM Local Bus DDR MPC8533E PCIe 10/100/1000 Expansion ...
Page 122
... Figure 1-6. Security Appliance Enabled by SEC, local bus, PCI, and Ethernet MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-24 DDR/DDR-2 Flash Flash SDRAM Local Bus MPC8533E SEC PCI/PCIe System Interface DDR S/RGMII 10/100/1000 Ethernet Protected Connection Freescale Semiconductor ...
Page 123
... MPC8533E SAN host adapter enabled by local bus, PCI Express, and Ethernet. Local Bus SATA II PCIe PCIe RAID Controller Figure 1-7. IP SAN Host Adapter enabled by local bus, PCI Express, and Ethernet MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor DDR/DDR-2 SDRAM Flash DDR S/RGMII MPC8533E S/RGMII XOR ...
Page 124
... TDM MSC81xx2 DSP Figure 1-8. VoIP Aggregation Application Enabled by local bus and Ethernet MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-26 Compact DDR/DDR-2 Flash Flash SDRAM Local Bus R/GMII MPC8533E DDR S/RGMII 10/100/1000 Ethernet Backplane/Network Interfaces Freescale Semiconductor ...
Page 125
... PCI Express 1 PCI Express 3 Local bus DDR SDRAM 1 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 2-1. Target Interface Codes Target Interface The general intent of the Target Interface Codes is to maintain consistency across PowerQUICC III family devices. ...
Page 126
... Table 2-2. Local Access Windows Example Base Address Size 0x0_0000_0000 2 Gbytes 0x0_8000_0000 1 Mbyte 0x0_A000_0000 256 Mbytes 0x0_C000_0000 256 Mbytes 0x8_0000_0000 32 Gbytes Unused 0x0_A000_0000 PCI 0x0_B000_0000 0x0_C000_0000 Local Bus Target Interface 0b1111 (DDR SDRAM) 0b0100 (local bus) 0b0000 (PCI) 0b0100 (local bus) 0b0100 (PCI Express) Freescale Semiconductor ...
Page 127
... High-order address bits defining location of the window in the initial address space Window size/attributes Window enable, window size, target interface, and transaction attributes MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Location”). However, note that the e500 core only Table 2-3 Function ...
Page 128
... The local access window registers exist as part of the local access block in the general utilities registers. See Section 2.3.4, “General Utilities Registers.” MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-4 Section 2.1, “Local Memory Map Overview and A detailed description of the local access window for and Freescale Semiconductor ...
Page 129
... LAWAR8—Local access window 8 attribute register 0x0_0D28 LAWBAR9—Local access window 9 base address register 0x0_0D30 LAWAR9—Local access window 9 attribute register MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Register Memory Map Access Reset Section/Page R 0x0000_0000 2 ...
Page 130
... MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-6 Figure 15 16 All zeros Table 2-5. LAIPBRR1 Field Descriptions Description Figure IP_INT All zeros Table 2-6. LAIPBRR2 Field Descriptions Description 2-2. Access: Read only 23 24 IP_MJ IP_MN 2-3. Access: Read only 23 24 IP_CFG Freescale Semiconductor 31 31 ...
Page 131
... The local access window n is enabled and other LAWAR n and LAWBAR n fields combine to identify an address range for this window. 1–7 — Write reserved, read = 0 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 8 BASE_ADDR All zeros Table 2-7. LAWBAR n Field Descriptions Description ...
Page 132
... MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-8 Description bytes Table 2-9, local access window 1 governs the mapping of the 1-Mbyte Size 1 Mbyte 0b0100 (Local bus controller —LBC) 2 Gbytes 0b1111 (DDR SDRAM) (SIZE+1) bytes. Target Interface Freescale Semiconductor ...
Page 133
... Inbound address translation and mapping refers to the translation of an address from the external address space of an I/O interface (such as PCI address space) to the local 36-bit address space understood by the MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Section 18.3.5.1, “PCI Express Outbound ATMU Registers” Memory Map ...
Page 134
... When the local e500 processor is used to configure CCSR space, the CCSR memory space should typically be marked as cache-inhibited and guarded. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-10 for a detailed description of the PCI Express inbound ATMU NOTE Section 17.3.1.3, “PCI ATMU Section 18.3.5.1, “PCI Section 4.3.1.1.2, The default value for Freescale Semiconductor ...
Page 135
... Table 2-10. Local Memory Configuration, Control, and Status Register Summary Offset from CCSRBAR 0x0_0000–0x3_FFFF 0x4_0000–0x7_FFFF 0x8_0000–0xB_FFFF 0xC_0000–0xD_FFFF 0xE_0000–0xF_FFFF MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Register Grouping General utilities Programmable interrupt controller (PIC) Reserved Reserved Device-specific utilities Memory Map Section 17.3.2.11, “ ...
Page 136
... DMA 0x2 4000 eTSEC 1 0x2 5000 0x2 6000 eTSEC 3 0x2 7000 0x3 0000 SEC 0x3 FFFF and Status Memory Block General Utility Block 0xn n000 General Registers 0xn nC00 ATMU 0xn nE00 Error Mgmt 0xn nF00 Debug Freescale Semiconductor ...
Page 137
... Also, when reading from a register, software should not rely on the value of any reserved bit remaining consistent. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE PIC Registers ...
Page 138
... PowerQUICC III TSECs. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-14 0xE 0000 0xE 1000 0xE 2000 0xF FFFC and Status Memory Block NOTE Device-Specific Registers Global Utilities Perf. Monitor Watchpoint/Debug Freescale Semiconductor ...
Page 139
... Reserved 0x2_6000 eTSEC3 0x2_7000– Reserved 0x3_0FFF MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 2-11. CCSR Block Base Address Map Block Section/Page General Utilities (0x0_0000–0x3_FFFF) 17.3/17-11 15.5/15-12 15.5/15-12 Comments 4.3.1/4-4 0x0_0000: Configuration, control, ...
Page 140
... Watchpoint Monitor and Trace Buffer 0xE_3000– Reserved 0xF_FFFF MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-16 Block Section/Page 12.2/12-10 10.3.1/10-18 10.3.7/10-39 10.3.8/10-44 Reserved (0x8_0000–0xD_FFFF) Device Specific Utilities (0xE_0000–0xF_FFFF) 19.4/19-3 20.3/20-3 21.3/21-9 Comments Freescale Semiconductor ...
Page 141
... Note that these figures show multiplexed signals multiple times. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE illustrate the external signals of the MPC8533E, showing how the ...
Page 142
... LSSD_MODE L1_TSTCLK L2_TSTCLK TEST_SEL TEMP_ANODE, TEMP_CATHODE TCK TDI TDO TMS TRST SD1_TX[7:0], SD1_TX[7:0] SD1_RX[7:0], SD1_RX[7:0] SD1_REF_CLK, SD1_REF_CLK SD2_TX[3:0], SD2_TX[3:0] SD2_RX[3:0], SD2_RX[3:0] SD2_REF_CLK, SD2_REF_CLK UART_SIN[0:1] UART_SOUT[0:1] UART_CTS[0:1] UART_RTS[0:1] Freescale Semiconductor Gen. Purpose Clock Test JTAG SerDes Interface 1 SerDes Interface 2 Dual UART Interface ...
Page 143
... EC_GTX_CLK125 Ethernet PIC IRQ9/DMA_DREQ3 Interface IRQ10/DMA_DACK3 IRQ11/DMA_DDONE3 UART_SOUT[0:1] Dual UART UART_CTS[0:1] Interface UART_RTS[0:1] Figure 3-2. MPC8533E Signal Groupings (2/3) (Continued) MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 1 1 EC_MDC 1 EC_MDIO MCP 1 1 UDE 1 1 IRQ[0: IRQ_OUT ...
Page 144
... LDP[0:3] cfg_cpu_boot/LA[27 cfg_sys_pll[0:3]/LA[28:31 cfg_sec_freq/LWE0/LBS0 3 LCS[0:4] 5 cfg_host_agt[0:2]/LWE[1:3]/LBS[1: cfg_core_pll[0]/LBCTL 1 1 cfg_core_pll[1]/LALE 1 1 cfg_core_pll[2]/LGPL2/LOE/LSDRAS cfg_dram_type[0]/LGPL0/LSDA10 1 1 cfg_dram_type[1]/LGPL1/LSDWE 1 1 cfg_boot_seq[0]/LGPL3/LSDCAS 1 1 cfg_boot_seq[1]/LGPL5 cfg_mem_debug/MSRCID[ cfg_ddr_debug/MSRCID[ LCKE 1 LCLK[0: Configuration Freescale Semiconductor ...
Page 145
... PCI initiator ready PCI_STOP PCI stop PCI_DEVSEL PCI device select PCI_IDSEL PCI initial device select MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 3-1 lists signals grouped by function, Functional Alternate Function(s) Block DDR memory — DDR memory — ...
Page 146
... I/O Signals Page 1 I/O 17-2/17-6 1 I/O 17-2/17-6 1 I/O 17-2/17 17-2/17-6 1 I/O 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17-6 1 I/O 17-2/17 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15-9 1 I/O 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15-9 Freescale Semiconductor ...
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... Local bus UPM general purpose line 0 LGPL1 Local bus GP line 1 LGPL2 Local bus GP line 2 /LOE /output enable MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Signal Reference by Functional Block (continued) Functional Alternate Function(s) Block eTSEC3 FIFO3_TXD[6:4] /cfg_io_ports[0:2] eTSEC3 ...
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... Page 1 O 14-2/14-5 1 I/O 14-2/14 14-2/14 14-2/14 14-2/14 14-2/14 14-2/14 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 10-5/10 10-5/10 10-5/10 10-5/10 10-5/10 10-5/10 10-5/10 13-2/13 13-2/13 13-2/13 13-2/13-3 1 I/O 11-2/11-4 1 I/O 11-2/11-4 1 I/O 11-2/11-4 1 I/O 11-2/11 18-2/18-5 Freescale Semiconductor ...
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... LSSD_MODE LSSD mode L1_TSTCLK L1 test clock L2_TSTCLK L2 test clock TEST_SEL Test select MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Signal Reference by Functional Block (continued) Functional Alternate Function(s) Block PCI Express 2 — PCI Express 1 — PCI Express 2 — ...
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... O 19-2/19-2 — 16-3/16-6 LCS6 1 O 16-3/16-6 IRQ10 1 O 16-3/16-6 — 16-3/16-6 LCS7 1 O 16-3/16-6 IRQ11 1 O 16-3/16-6 — 16-3/16-6 LCS5 1 I 16-3/16-6 IRQ9 1 I 16-3/16-6 — 17-2/17-6 — 17-2/17-6 — 1 I/O 17-2/17-6 — 19-2/19-2 19.4.1.9/19-12 — 19-2/19-2 19.4.1.9/19-12 Freescale Semiconductor ...
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... Local bus GP line 3 LGPL4 Local bus GP line 4 /LGTA/ /GPCM terminate access LUPWAIT /UPM wait LGPL5 Local bus GP line 5 address MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block System control — System control — — ...
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... No. of Table/ I/O Signals Page 1 I 21-5/21 14-2/14 14-2/14 14-2/14 14-2/14 9-3/9 9-3/9 9-3/9 9-3/9 9-3/9 10-5/10 9-3/9 9-3/9 9-3/9-5 64 I/O 9-3/9-5 8 I/O 9-3/9-5 9 I/O 9-3/9-5 1 I/O 9-3/9 21-3/21-6 8 I/O 9-3/9 9-3/9 21-3/21 21-3/21 21-3/21 9-3/9-5 32 I/O 17-2/17-6 Freescale Semiconductor ...
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... SerDes2 reference clock complement SD2_RX[0], Receive data, SD2_RX[0] receive data complement SD2_TX[0], Transmit data, SD2_TX[0] transmit data complement MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block PCI — PCI — PCI — PCI — ...
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... Table/ I/O Signals Page 1 I 4-2/4 4-3/4 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-4/21 21-4/21 21-5/21 15-2/15-9 1 I/O 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15-9 1 I/O 15-2/15 15-2/15 15-2/15-9 Freescale Semiconductor ...
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... For details about all the signals that require external pull-up resistors, see the MPC8533E Integrated Processor Hardware Specifications. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) ...
Page 156
... Indeterminate if not driven (no default) cfg_cpu_boot 1 cfg_sys_pll[0:3] Must be driven cfg_host_agt[0:2] 111 cfg_core_pll[0] Must be driven cfg_core_pll[1] Must be driven cfg_core_pll[2] Must be driven cfg_dram_type[0] 1 cfg_dram_type[1] 1 cfg_boot_seq[0] 1 cfg_boot_seq[1] 1 cfg_mem_debug 1 cfg_ddr_debug 1 Freescale Semiconductor ...
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... TSEC3 TSEC3 TSEC3 TSEC3 TSEC3 LBC LBC LBC LBC DMA DMA MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor for a complete description of the reset functionality. Signal MBA[2:0] MA[15:0] MWE MRAS MCAS MCS[0:3] MCKE[0:3] MCK[0:5], MCK[0:5] MODT[0:3] SD_TX[7:0], SD_TX[7:0] ...
Page 158
... Input—reset config (test only) MDVAL ASLEEP Input—reset config (test only) CLK_OUT GPOUT[0:7] TDO Section 4.4.3.9, “DDR SDRAM Type,” on page 4-17 State During Reset High-Z 2 Driven (test only) High-Z High-Z High-Z 2 High High-Z 2 Driven Toggling High-Z Driven Freescale Semiconductor ...
Page 159
... Second SERDES high-speed interface reference clock SD2_REF_CLK The following sections describe the reset and clock signals in detail. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor contains references to additional sections that contain more information. Table 4-1. Signal Summary Description ...
Page 160
... TOSR[SEL] equals 0b000. See Section 4.4.2, “Power-On Reset Sequence,” Subsequent assertion/negation due to power down modes occurs asynchronously. Section 4.4.3, “Power-On Reset and Section 4.4.3, “Power-On Section 11.4.5, “Boot Chapter 21, “Debug Features and Watchpoint for more information. Freescale Semiconductor ...
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... Timing Assertion/Negation—See the MPC8533E Integrated Processor Hardware Specifications for specific timing information for this signal. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Reset, Clocking, and Initialization Description Section 4.4.4.4, “Real Time Clock.” ...
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... The effect of the update must be guaranteed to be visible by the MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-4 Register Access Reset Section/Page R/W 0x000F_F700 4.3.1.1.2/4-5 R/W 0x0000_0000 4.3.1.2.1/4-6 R/W 0x0000_0000 4.3.1.2.1/4-6 R/W 0x0000_0000 4.3.1.3.1/4-7 Freescale Semiconductor ...
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... BASE_ADDR Identifies the16 most-significant address bits of the window used for configuration accesses. The base address is aligned on a 1-Mbyte boundary. 24–31 — Write reserved, read = 0 MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 7 8 BASE_ADDR 1 Table 4-5. CCSRBAR Bit Settings ...
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... Figure 4-3. Alternate Configuration Attribute Register (ALTCAR) MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-6 for more information. NOTE 7 8 BASE_ADDR All zeros Table 4-6. ALTCBAR Bit Settings Description TRGT_ID All zeros Access: Read/Write — Access: Read/Write 31 — Freescale Semiconductor ...
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... R EN — W Reset Figure 4-4. Boot Page Translation Register (BPTR) MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-7. ALTCAR Bit Settings Description 1001–1010 Reserved 1011 Security 1100 Reserved 1101 Reserved 1110 Reserved 1111 Local memory —DDR SDRAM and on-chip Section 4.4.3.4, “ ...
Page 166
... Section 4.4.3.8, “Boot Sequencer Configuration.” Section 11.4.5, “Boot Sequencer Mode,” for more information on the setting of the soft reset flag. Note that interface and writes data to The boot sequencer the I C chapter. Section 19.4.1.14, “Machine Check Section 4.4.2, Freescale Semiconductor If the ...
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... When PLL locking is completed, the boot sequencer is released, causing it to load configuration data from serial ROMs, if enabled, as described in Configuration.” MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Mode,” and Section 11.4.5.2, “EEPROM Data Section 19.4.1.18, “Reset Control Register NOTE: Section 4.4.3.8, “ ...
Page 168
... MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-10 Section 4.4.3.7, “CPU Boot Configuration.” Section 21.3.4.1, “Trigger Out Source Register (TOSR),” Section 21.3.4, “Trigger Out Function.” Section 19.4.1, “Register Descriptions.” Figure 4-5. Power-On Reset Sequence The for more For more Freescale Semiconductor ...
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... Note that the values latched on these signals during POR are accessible in the PORPLLSR (POR PLL status register), as described in (PORPLLSR).” MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE Table 4-9, establish the clock ratio between the SYSCLK input and the Section 19.4.1.1, “ ...
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... HID1 register, as Table 4-10. e500 Core Clock PLL Ratios Reset Configuration Name Value (Binary) cfg_core_pll[0:2] CCB Clock : SYSCLK Ratio Reserved Reserved Reserved Reserved Reserved Reserved Reserved e500 Core: CCB ClockRatio 000 001 Reserved 010 011 (1 100 101 (2.5:1) 110 111 (3 Freescale Semiconductor ...
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... Note that the values latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in Register (PORBMSR).” MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-11, is used to establish the ratio of the e500 Core Table 4-11. SEC Mode Configuration ...
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... PCI/PCI-Express interfaces. 110 MPC8533E acts as an agent of an external host on its PCI interface. It acts as a root complex for all PCI-Express interfaces. 111 MPC8533E acts as the host processor/root complex on all interfaces (default). Chapter 17, “PCI respectively. Meaning Table 4-14 shows the configuration of Freescale Semiconductor ...
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... The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in the ECM CCB port configuration register (EEBPCR). See Register (EEBPCR),” for more information. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-14. I/O Port Selection Value (Binary) 000 ...
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... C addressing mode is used. Boot sequencer is enabled and loads configuration information from a ROM on the I ROM must be present. 11 Boot sequencer is disabled NOTE Section 4.4.3.7, “CPU Boot Meaning Section 11.4.5, Meaning 2 C interface. A valid 2 C1 interface. A valid 2 C ROM is accessed (default). Configuration.” Freescale Semiconductor ...
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... The value of this configuration setting does not affect the width of the FIFO interface on eTSEC3, which is always 8 bits. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-17 describes the configuration of the DDR Table 4-17. DDR DRAM Type ...
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... The eTSEC1 controller operates using the TBI protocol (or RTBI if configured in reduced mode as described in Width”) (default). Table 4-21, select the protocol (FIFO, MII, GMII or TBI) used by Meaning Section 19.4.1.4, “POR Device Meaning Section 4.4.3.10, “eTSEC1 Section 4.4.3.10, “eTSEC1 Section 4.4.3.10, “eTSEC1 Section 19.4.1.4, “POR Device Freescale Semiconductor ...
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... Section 19.4.1.4, “POR Device Status Register (PORDEVSR).” Functional Signal Reset Configuration Name PCI_GNT[3] cfg_pci_speed Default (1) MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-21. eTSEC3 Protocol Configuration Value (Binary) 00 The eTSEC3 controller operates using 8-bit FIFO protocol. ...
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... Debug information from the local bus controller (LBC) is driven on the MSRCID and MDVAL signals 1 Debug information from the DDR SDRAM controller is driven on the MSRCID and MDVAL signals (default). Table 4-27, enables a DDR memory controller debug mode select the impedance of the PCI I/O Meaning Meaning Meaning Freescale Semiconductor ...
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... Alternately, a separate, independent clock may be used for the PCI interface, in which case PCI operation is asynchronous with respect to SYSCLK and the platform clock. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-27. DDR Debug Configuration Value ...
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... CCB_clk to Rest of the Device Table 4-29. Table 4-29. High Speed Interface Clocking Bit Rate Reference Clock Frequency 2.5 Gbps 100 MHz (Spread Spectrum supported) × ( PCI Express link width 8 core_clk 6 MCK[0:5] 6 MCK[0:5] LSYNC_IN LSYNC_OUT LCLK0 LCLK1 LCLK2 ) Freescale Semiconductor DDR Controller LBC ...
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... Section 10.3.2.6, “Timer Control Register signal to clock the global timers in the PIC unit. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor (TCR),” provides additional information on the use of the RTC Reset, Clocking, and Initialization Section 4.4.3.1, ...
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... Figure 4-7. RTC and Core Timer Facilities Clocking Options MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-24 HID0 TBEN TBL 32 63 • • • Core Timer Facilities Clock • • • (Decrementer) DEC Auto-Reload DECAR 32 63 SEL_TBCLK RTC (Sampled ÷ 8 CCB Clock Freescale Semiconductor ...
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... The e500 core complex interacts with the L2 cache through the core complex bus (CCB). MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor provides an overview of the e500v2 core processor and the provides a listing of the e500v2 registers in reference form. ...
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... Core Complex and L2 Cache MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 II-2 Freescale Semiconductor ...
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... Note that this conceptual diagram does not attempt to show how these features are physically implemented. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 5-1 ...
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... Core Complex Overview Figure 5-1. e500 Core Complex Block Diagram MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-2 Freescale Semiconductor ...
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... Customer software that uses SPE or embedded floating-point instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libcfsl_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices. 5.1.2 ...
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... Version Register (PVR),” (SVR)”). Processor Version Register (PVR) 0x8021_0021 0x803C_0010 for MPC8533E (with security) 0x8034_0010 for MPC8533 (without security) 0x8021_0022 0x803C_0011 for MPC8533E (with security) 0x8034_0011 for MPC8533 (without security) Section 6.5.3, “Processor System Version Register (SVR) Freescale Semiconductor ...
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... Figure 5-2. Original SPE Definition MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Section 5.8, “Interrupts and Exception Handling.” NOTE Vector and Floating-Point APUs SPE vector instructions ev… Vector single-precision floating-point evfs… ...
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... Dynamic branch prediction using a 512-entry, 4-way set-associative branch target buffer (BTB) supported by the e500 BTB instructions listed in — Branch prediction is handled in the fetch stages. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-6 Figure 5-7. SPE instructions are grouped as follows: Table Table 5-3 5-5. Freescale Semiconductor ...
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... Note that although most divide instructions take more than 4 cycles to execute, the MU allows subsequent multiply instructions to execute through all four MU stages in parallel with the divide. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figure 5-3. From GIQ0 or GIQ1 ...
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... Station Load/Store Unit (64-/32-Bit) Three-Stage Pipeline Queues and Buffers Load L1 Store Queue Miss Queue Data Line Fill Buffer Data Write e500v1 (3 entry) Buffer e500v2 (5 entry) To core interface unit Figure 5-4. Three-Stage Load/Store Unit To data cache e500v1 (4 entry) e500v2 (9 entry) Freescale Semiconductor ...
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... Support for big-endian and true little-endian memory on a per-page basis • Power management — Low-power design MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Core Complex Overview effective address space physical memory on the e500v1 and 64 ...
Page 194
... PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions required to flush the cache. Detailed descriptions of these differences are provided in their respective chapters. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-10 Freescale Semiconductor ...
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... Scalar single-precision floating-point instructions use only the lower 32 bits of the GPRs; double-precision operands (e500v2 only) use all 64 bits. floating-point instructions. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE - then-else statement that selects between two source registers by Table 5-2 lists performance monitor instructions ...
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... Freescale Semiconductor ...
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... MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 5-5. BTB Locking Instructions Name Mnemonic ...
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... General Issue Queue (GIQ) Execute Stage MU Stage 1 Divide Bypass Stage 2 Divide Postdivide Stage 3 Stage 4 Maximum two-instruction Completion Stage completion per clock cycle Write-Back Stage Figure 5-5. Instruction Pipeline Flow 5-5. Instruction Cache Maximum four-instruction fetch per clock cycle SU2 SU1 Freescale Semiconductor ...
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... SU2 increases the availability of SU1 to execute more computational-intensive instructions. An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU instruction in GIQ0 that is stalled behind a long-latency divide. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor From IQ0/IQ1 GIQ3 GIQ2 To SU2, MU, or LSU ...
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... Programming Model The following section describes the e500 core registers. MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-16 Figure 5-7 shows the e500 register set. Freescale Semiconductor ...