MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 560

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
For the F8 function, for example, if the 64-bit F8 keystream is 0x1234567890ABCDEF and the data size
register contains 0x0a (10 = 1 byte + 2 bits), the final ten message bits will be exclusive-ORed (XORed)
with ten bits of keystream 0x120. The PE (process end of message) mode bit must be set.
For the 3GPP F9 function: The final 64 bits of the message will be padded as specified in the 3GPP F9
algorithm. The PE (process end of message) mode bit must be set.
3GPP F9 padding is automatically performed. The CD (communication direction) bit (see
and 1 is appended to the end of the message. The result is then zero-padded to 64 bits.
For example, if the last block is xF81A_0000_0000_0000 (big endian) and data size contains 0x0F (15 bits
= 1 byte + 7 bits), the word (0xF81A = 1111_1000_0001_1010) the most-significant 15 bits (underlined)
are padded left to right as follows:
1111_1000_0001_101$_1000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
where $ is the value of the CD (communication direction) bit in the mode register.
12.4.7.4
The KEU reset control register, shown in
the 3 self-clearing bits:
Table 12-45
0–60
12-82
Bits
Address KEU 0xE010
Address KEU 0xE018
61
Reset
Reset
W
W
R
R
Name
—
0
RI
0
describes the KEU reset control register fields.
KEU Reset Control Register (KEURCR)
Reserved
Reset interrupt. Writing this bit active high causes KEU interrupts signaling DONE and ERROR to be reset. It
further resets the state of the KEU interrupt status register.
0 Don’t reset
1 Reset interrupt logic
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-45. KEU Reset Control Register Field Descriptions
Figure 12-60. KEU Reset Control Register
Figure 12-59. KEU Data Size Register
Figure
—
12-60, allows 3 levels of reset of the KEU, as defined by
All zeros
All zeros
Description
47 48
Freescale Semiconductor
Data Size (bits)
Access: Read/write
Access: Read/write
60
Table
RI
61
12-49)
MI
62
SR
63
63