MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 942

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
16.2.2
Table 16-3
16.3
This section provides a detailed description of all accessible DMA memory and registers. The descriptions
include individual bit level descriptions and reset states of each register. Undefined 4-byte address spaces
within offset 0x000–0xFFF are reserved.
Table 16-4
programmable CCSRBAR together with the fixed DMA block base address and offset listed in
In this table and in the register figures and field descriptions, the following access definitions apply:
16-6
DMA_DDONE n O DMA done. Indicates that a DMA transfer is complete
DMA_DACK n
DMA_DREQ n
DMA request
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
Memory Map/Register Definition
lists the DMA registers and their offsets. Note that the full register address is comprised of the
describes the DMA signals.
Detailed Signal Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O DMA acknowledge. Indicates that a DMA transfer is currently in progress
I DMA request. The DMA request signal indicates the start of a DMA transfer or a restart from a paused
request. Assertion of DMA_DREQ n causes MR n [CS] to be set, thereby activating the corresponding
DMA channel.
Meaning
Meaning
Meaning
Timing Assertion—Can be asserted asynchronously
Timing Assertion—Asynchronous assertion; asserted for more than three system clocks
Timing Assertion—Always asserts asynchronously after the negation of the final DMA_DACK n to
State
State
State
Table 16-3. DMA Signals—Detailed Signal Descriptions
Asserted—Assertion of DMA_DREQ n while DMA_DACK n is negated causes a new transfer
Negated—Negation while DMA_DACK n is asserted has no effect. Negation before the
Negation— Must remain asserted at least until the assertion of the corresponding
Asserted—Indicates that a DMA transfer is currently in progress. Asserted after the assertion
Negated—Negated after finishing a complete transfer or after entering a paused state if
Negation—Asynchronous negation; negated for more than three system clocks
Asserted—Indicates transfer completion. SRn[CB] is clear. Note, however, that write data
Negated—Indicates that the current transfer is in process
Negation—Negated asynchronously after the assertion of DMA_DREQ n for the next transfer
to start OR resumes a paused transfer if the EMP_EN bit is set. Assertion while
DMA_DACK n is asserted results in an illegal condition.
assertion of DMA_DACK n results in an illegal condition.
DMA_DACK n
of DMA_DREQ n to indicate the start of a transfer
MR n [EMP_EN] is set
may still be queued at the target interface or in the process of transfer on an external
interface.
indicate completion of a transfer. For a paused transfer, DMA_DDONE n is asserted
asynchronously after the negation of the final DMA_DACK n .
Description
Freescale Semiconductor
Table
16-4.