MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 716

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
bus has to use read-modify-write cycles and compromise performance, SRAM banks can be used with
natural parity and do not compromise performance for parity support.
14.5.6
Interfacing to DSP Host Ports
In many applications, an integrated communications processor aggregates traffic for DSPs and distributes
that traffic to the DSPs. The local bus allows connection to a variety of different DSP host ports and this
section gives some information on how to interface to some example DSPs.
14.5.6.1
Interfacing to MSC8101 HDI16
This section describes how to interface to the HDI16 peripheral interface of the MSC8101. After initial
set-up of the interface, the host and HDI16 device can communicate either by a read and write transaction
from the core or, if the setup on the DSP and the host are implemented appropriately, by DMA transfers
of the host DMA controller, which can be triggered automatically by signals generated by the HDI16
peripheral.
14.5.6.1.1
HDI16 Peripherals
The host interface (HDI16) is a 16-bit-wide, full-duplex, double-buffered parallel port that can directly
connect to the data bus of a host processor. It supports a variety of buses and gluelessly connects with a
number of industry-standard microcomputers, microprocessors, and DSPs. The HDI16 also supports the
8-bit host data bus, which makes it fully compatible with the DSP56300 HI08 (as viewed by the host side,
not from the DSP side).
The host bus can operate asynchronously to the SC140 core clock, and the HDI16 registers are divided
into two banks. The host register bank is accessible to the external host, and the core register bank is
accessible to the SC140 core.
The MSC8101HDI16 host port peripheral has two sets of 16-bit-wide registers—one set is only visible
internally to the DSP, while the other set is visible only to the external host processor.
Figure 14-81
illustrates the relationship between the two sides.
All of the HDI16 peripheral’s registers are mapped directly onto the MSC8101 QBus, as defined by the
MSC8101 16-Bit Digital Signal Processor Reference Manual (MSC8101RM); the transmit and receive
FIFOs are mapped onto the DMA data bus such that the DMA controller can access them directly without
core intervention. The addressing for each of these registers is defined in
Section 14.5.6.1.2, “Physical
Interconnections.”
The HDI16 host port itself is a 16-bit-wide parallel port with various strobe and multiplexing options.
The most important HDI16 host port facet is that it is specified as an asynchronous interface and so reduces
concerns over clock skew between the HDI16 host port and the host device’s buses. Furthermore, with all
the host port registers being accessed with a single chip select and four address lines, as far as the local bus
is concerned, the DSP host port is akin to an asynchronous memory mapped region. So, for the HDI16 port
in single strobe mode, the host device asserts a chip select, a single data strobe and a read/write line to
select HDI16 read or write bus operations.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
14-98
Freescale Semiconductor