MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 369

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

By using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence detect
capability of memory modules, system firmware uses the memory-boundary registers to configure the
DDR memory controller to map the size of each bank in memory. The memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank starting
and ending addresses. The memory banks are not required to be mapped to a contiguous address space.
9.5.2
Table
configuration. The address presented at the memory controller signals MA[15:0] use MA[15] as the msb
and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit in DDR1/DDR2 modes for reads and
writes, so the column address can never use MA[10].
Freescale Semiconductor
16 x 11
16 x 10
15 x 11
15 x 10
14 x 11
14 x 10
13 x 11
13 x 10
x 2
x 2
x 2
x 2
x 2
x 2
x 2
x 2
Row
Col
9-40,
x
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MBA
MBA
MBA
MBA
MBA
MBA
MBA
MBA
Table 9-40. DDR1 Address Multiplexing for 64-Bit Data Bus with Interleaving Disabled
Table 9-41 Table
DDR SDRAM Address Multiplexing
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
msb
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 12 11 10 9
13 12 11 10 9
12 11 10 9
12 11 10 9
9-42, and
8
8
Table 9-43
7
8
7
8
6
7
6
7
5
6
5
6
Address from Core Master
4
5
4
5
show the address bit encodings for each DDR SDRAM
4
3
4
3
2
3
2
3
1
2
1
2
0
1
0
1
1 0
1 0
1
0
1
0
1 0
1 0
0
1
0
1
11 9 8 7 6 5 4 3 2 1 0
11 9 8 7 6 5 4 3 2 1 0
11 9
11 9
0
0
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
9
9
8
8
8
8
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
DDR Memory Controller
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
lsb
9-47