MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 37

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
18.3.2.3
18.3.2.4
18.3.2.5
18.3.3
18.3.3.1
18.3.3.2
18.3.3.3
18.3.3.4
18.3.4
18.3.4.1
18.3.4.2
18.3.5
18.3.5.1
18.3.5.1.1
18.3.5.1.2
18.3.5.1.3
18.3.5.1.4
18.3.5.2
18.3.5.2.1
18.3.5.2.2
18.3.5.2.3
18.3.5.2.4
18.3.5.2.5
18.3.5.2.6
18.3.6
18.3.6.1
18.3.6.2
18.3.6.3
18.3.6.4
18.3.6.5
18.3.6.6
18.3.6.7
18.3.6.8
18.3.7
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Power Management Event and Message Registers ............................ 18-13
PCI Express IP Block Revision Registers ............................................................... 18-18
PCI Express ATMU Registers ................................................................................. 18-19
PCI Express Error Management Registers .............................................................. 18-29
PCI Express Configuration Space Access ............................................................... 18-42
PCI Express Outbound Completion Timeout Register
PCI Express Configuration Retry Timeout Register
PCI Express Configuration Register (PEX_CONFIG)........................................ 18-12
PCI Express PME and Message Detect Register (PEX_PME_MES_DR) ......... 18-13
PCI Express PME and Message Disable Register
PCI Express PME and Message Interrupt Enable Register
PCI Express Power Management Command Register (PEX_PMCR) ................ 18-17
IP Block Revision Register 1 (PEX_IP_BLK_REV1)........................................ 18-18
IP Block Revision Register 2 (PEX_IP_BLK_REV2)........................................ 18-19
PCI Express Outbound ATMU Registers ............................................................ 18-19
PCI Express Inbound ATMU Registers ............................................................... 18-24
PCI Express Error Detect Register (PEX_ERR_DR).......................................... 18-29
PCI Express Error Interrupt Enable Register (PEX_ERR_EN) .......................... 18-32
PCI Express Error Disable Register (PEX_ERR_DISR) .................................... 18-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT) ............... 18-35
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)............................ 18-36
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)............................ 18-38
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)............................ 18-39
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)............................ 18-40
(PEX_OTB_CPL_TOR).................................................................................. 18-11
(PEX_CONF_RTY_TOR)............................................................................... 18-11
(PEX_PME_MES_DISR) ............................................................................... 18-14
(PEX_PME_MES_IER) .................................................................................. 18-16
PCI Express Outbound Translation Address Registers (PEXOTARn) ........... 18-20
PCI Express Outbound Translation Extended Address Registers
PCI Express Outbound Window Base Address Registers
PCI Express Outbound Window Attributes Registers (PEXOWARn)............ 18-22
EP Inbound ATMU Implementation................................................................ 18-24
RC Inbound ATMU Implementation............................................................... 18-25
PCI Express Inbound Translation Address Registers (PEXITARn)................ 18-25
PCI Express Inbound Window Base Address Registers (PEXIWBARn) ....... 18-26
PCI Express Inbound Window Base Extended Address Registers
PCI Express Inbound Window Attributes Registers (PEXIWARn) ................ 18-27
(PEXOTEARn)............................................................................................ 18-21
(PEXOWBARn) .......................................................................................... 18-21
(PEXIWBEARn) ......................................................................................... 18-27
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