MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1231

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

21.2.2.2
Table 21-4
Freescale Semiconductor
MSRCID[0:4]
MECC[0:7]
Signal
TRIG_IN
Signal
shows detailed descriptions of the watchpoint monitor and trace buffer signals.
Watchpoint Monitor Trigger Signals—Details
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 21-3. Debug Signals—Detailed Signal Descriptions (continued)
Table 21-4. Watchpoint and Trigger Signals—Detailed Signal Descriptions
I/O
O Memory ECC. DDR error checking and correcting. The normally bidirectional operation of the
O Memory source ID. Attribute signals associated with the memory interface that indicate the
I/O
I Trigger in. Can be used to trigger the watchpoint and trace buffers. Note this is an active-high
memory ECC (MECC) bus is described in
(ECC).”
In debug mode, the high-order 5 bits (MECC[0:4]) may be used to provide the transaction
source ID and MECC5 can be used as the data-valid indicator.
In debug mode, MECC[0:5] is constantly driven with debug information and must be
disconnected from the DDR memory’s ECC pins.
source ID for a transaction on an SDRAM interface. The SDRAM interface, DDR or local bus,
to which the debug information applies is specified during POR with MSRCID0 as shown in
Table
Meaning
Meaning
(rising-edge triggered) signal.
Meaning
Timing Driven every cycle in debug mode.
Timing Driven every cycle in debug mode. Similar timing to MA.
Timing Assertion/Negation—The MPC8533E interprets TRIG_IN as asserted on detection of
State
State
State
21-1. Two of these signals serve as reset configuration input signals.
This bus is used for debug functions when MSRCID1 is sampled low during POR.
Asserted/Negated—In debug mode, MECC[0:5] is always driven. The source ID
Asserted/Negated—In debug mode, always driven with the value of the source ID.
Asserted—Indicates that a programmed/armed external event has been detected.
values appear during RAS and CAS cycles. A value of 0x1F (all ones) is driven
during cycles other than RAS and CAS. The data-valid indicator appears when
data is being received or driven on the pins.
The source ID has a value of 0x1F for cycles other than RAS and CAS. The
encodings shown in
transaction.
Assertion may be used internally to trigger trace buffers and watchpoint
mechanisms.
the rising edge. It may occur at any time. Must remain asserted for at least 3
system clocks to be recognized internally.
Table 21-26
Description
Section 9.5.11, “Error Checking and Correcting
Description
provide detailed information about a memory
Debug Features and Watchpoint Facility
21-7