MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 353

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 9-21
9.4.1.16
The DDR SDRAM initialization extended address register, shown in
address that will be used for the data strobe to data skew adjustment and automatic CAS to preamble
calibration after POR.
Table 9-22
Freescale Semiconductor
Offset 0x14C
Reset
28–31
Offset 0x148
Reset
0–31
1–27
Bits
Bits
0
W
R
W
R
UIA
0
0
INIT_EXT_ADDR Initialization extended address. Represents the extended address that will be used for the data
INIT_ADDR Initialization address. Represents the address that will be used for the data strobe to data skew
Name
describes the DDR_INIT_ADDR fields.
describes the DDR_INIT_EXT_ADDR fields.
1
Figure 9-16. DDR Initialization Address Configuration Register (DDR_INIT_ADDR)
Name
DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
UIA
—
Figure 9-17. DDR Initialization Extended Address Configuration Register
adjustment and automatic CAS to preamble calibration at POR. This address will be written to during
the initialization sequence.
Use initialization address.
0 Use the default address for training sequence as calculated by the controller. This will be the
1 Use the initialization address programmed in DDR_INIT_ADDR and DDR_INIT_EXT_ADDR.
Reserved, should be cleared.
strobe to data skew adjustment and automatic CAS to preamble calibration at POR. This extended
address will be written to during the initialization sequence.
Table 9-22. DDR_INIT_EXT_ADDR Field Descriptions
first valid address in the first enabled chip select.
Table 9-21. DDR_INIT_ADDR Field Descriptions
(DDR_INIT_EXT_ADDR)
—
INIT_ADDR
All zeros
All zeros
Description
Description
Figure
9-17, provides the extended
27 28
DDR_INIT_EXT_ADDR
DDR Memory Controller
Access: Read/Write
Access: Read/Write
9-31
31
31