MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 572

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Figure 12-73
notification via header writeback. A detailed description of the header dword fields used in writeback
notification is provided in
12-94
35–36
37–42
43–44
45–63
Writeback
8–34
Bits
Bits
0–7
61
62
63
Table 12-50. Crypto-Channel Configuration Register (CCCR) Field Descriptions (continued)
Name
CDIE Channel done interrupt enable.
DONE When done writeback is used, then at the completion of descriptor processing this byte is written with the
ICCR0 Integrity check comparison result from primary. These bits are supplied by the primary EU when descriptor
ICCR1 Integrity check comparison result from secondary. These bits are supplied by the secondary EU (if any) when
Name
NT
—
—
—
—
0
shows the format of the header dword when the channel is configured to perform done
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Notification type. This bit controls when the channel will generate channel done notification. Channel done
notification can take the form of an interrupt or modified header writeback or both, depending on the state of
the CDIE and CDWE control bits.
0 Global notification: The channel will generate channel done notification (if enabled) at the end of each
1 Selected notification: The channel will generate channel done notification (if enabled) at the end of every
0 Channel done interrupt disabled
1 Channel done interrupt enabled. Upon completion of descriptor processing, if the NT bit is set for global, or
Refer to
Reserved. Set to zero.
value 0xFF. To determine when done writeback is used, see the CDWE, NT, and CDIE fields in the channel
configuration register (see
Reserved.
processing is complete.
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Reserved.
descriptor processing is complete.
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Reserved.
DONE
descriptor.
descriptor with the DONE bit set in the descriptor header.
if the DN (done notification) bit is set in the header word of the descriptor, then notify the host by asserting
an interrupt.
Section 12.5.2, “Channel Interrupts,”
7
Table 12-51. Header Dword Writeback Field Descriptions
Table
8
Figure 12-73. Header Dword Writeback Format
12-51.
Table
—
12-51).
for complete description of channel interrupt operation.
34
Description
Description
35
ICCR0
36
37
—
42
43
ICCR1
44
Freescale Semiconductor
45
—
63