MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1206

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Device Performance Monitor
20.4.2
Using the control registers described in
the occurrences of specific events. The 64-bit PMC0 is designated to count only clock cycles. However,
to provide flexibility, a total of 64 reference events can be counted on any of the 32-bit PMCs
(PMC1–PMC9). Additionally, up to 64 unique events can be counted on each 32-bit counter.
The performance monitor must be reset before event counting sequences. The performance monitor can
be reset by first freezing one or more counters and then clearing the freeze condition to allow the counters
to count according to the settings in the performance monitor registers.þCounters can be frozen
individually by setting PMLCAn[FC] bits, or simultaneously by setting PMGC0[FAC]. Simply clearing
these freeze bits will then allow the performance monitor to begin counting based on the register settings.þ
Note that using PMLCAn[FC] to reset the performance monitor resets only the specified counter.
Performance monitor registers can be configured through reads or writes while the counters are frozen as
long as freeze bits are not cleared by the register accesses.
20.4.3
The threshold feature allows characterization of events that can take a variable number of clock cycles to
occur. Threshold events are counted only if the latency is greater than the threshold value specified in
PMLCBn[THRESHOLD]. There are two types of threshold events.
The first type of threshold events are duration threshold events. For duration threshold event sequences,
the PMC increments only when the duration of the event is equal to or greater than the threshold value.
The threshold value is scaled by a multiple specified in PMLCBn[TBMULT].
A duration threshold event requires two signals: The first indicates when a threshold event sequence
begins, and the second indicates when it ends. An internal counter determines when the threshold count is
exceeded and when the PMC can increment. This internal counter decrements during a threshold event
sequence until it reaches the value of one. A new sequence cannot begin until the current one completes.
Additional threshold start signals are ignored during a sequence until a threshold stop signal occurs. If both
a start and stop signal are asserted during the same cycle in a current sequence, the stop terminates the
current sequence and the start signals the beginning of a new one. However, if both signals are asserted
during the same cycle while not in a current event sequence, both signals are ignored.
timing diagram for duration threshold event counting.
An illegal condition exists if the threshold value obtained from PMLCBn[THRESHOLD] and
PMLCBn[TBMULT] is less than two. Under these conditions the intent of threshold counting is
ambiguous.
20-12
Event Counting
Threshold Events
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 20.3.2, “Control Registers,”
the twelve PMCs can count
Freescale Semiconductor
Figure 20-9
is a