MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 346

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
Table 9-13
9-24
11–15
16–19
20–26
9–10
Bits
4–5
6–8
0
1
2
3
DLL_RST_DIS
DQS_CFG
ODT_CFG
NUM_PR
FRC_SR
describes the DDR_SDRAM_CFG_2 fields.
SR_IE
Name
—
—
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Force self refresh
0 DDR controller will operate in normal mode.
1 DDR controller will enter self-refresh mode.
Self-refresh interrupt enable. The DDR controller can be placed into self refresh mode by forcing the
0 DDR controller will not enter self-refresh mode if panic interrupt is asserted.
1 DDR controller will enter self-refresh mode if panic interrupt is asserted.
0 DDR controller will issue a DLL reset to the DRAMs when exiting self refresh.
1 DDR controller will not issue a DLL reset to the DRAMs when exiting self refresh.
Reserved
DQS configuration
00 Only true DQS signals are used.
01 Differential DQS signals are used for DDR2 support.
10 Reserved
11 Reserved
Reserved
ODT configuration. This field defines how ODT will be driven to the on-chip IOs. See
Section 19.4.1.21, “DDR Control Driver Register (DDRCDR),”
that will be used. (DDR2-specific, must be cleared for DDR1)
00 Never assert ODT to internal IOs
01 Assert ODT to internal IOs only during writes to DRAM
10 Assert ODT to internal IOs only during reads to DRAM
11 Always keep ODT asserted to internal IOs
Reserved
at one time. Note that if posted refreshes are used, then this field, along with
DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum t
cannot be violated. For example, some DDR1 SDRAMs will not be able to use more than 3 posted
refreshes because the required refresh interval could then exceed the maximum constraint for t
0000 Reserved
0001 1 refresh will be issued at a time
0010 2 refreshes will be issued at a time
0011 3 refreshes will be issued at a time
...
1000 8 refreshes will be issued at a time
1001–1111Reserved
Reserved, should be cleared.
DLL reset disable. The DDR controller will typically issue a DLL reset to the DRAMs when exiting self
Number of posted refreshes. This will determine how many posted refreshes, if any, can be issued
PIC to assert IRQ_OUT. This is considered a ‘panic interrupt’ by the DDR controller, and it will
enter self refresh as soon as possible. DDR_SDRAM_CFG[SREN] must also be set if the panic
interrupt will be used.
refresh. However, this function may be disabled by setting this bit during initialization.
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions
Description
which defines the termination value
Freescale Semiconductor
ras
specification
ras
.