MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 134

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Memory Map
internal interfaces of the MPC8533E. It also refers to the mapping of transactions to a particular target
interface and the assignment of transaction attributes. The PCI and the PCI Express controllers have
inbound address translation and mapping units (ATMUs).
2.2.5.1
The PCI controller has three general inbound ATMU windows plus a dedicated window for memory
mapped configuration accesses (PCSRBAR). These windows have a one-to-one correspondence with the
base address registers in the PCI programming model. Updating one automatically updates the other. There
is no default inbound window; if a PCI address does not match one of the inbound ATMU windows, the
MPC8533E does not respond with an assertion of PCI_DEVSEL. See
Inbound Registers,”
2.2.5.2
The PCI Express controller has three inbound ATMU windows plus a default. See
Express Outbound ATMU Registers,”
windows.
2.2.5.3
Since both local access windows and inbound ATMUs map transactions to a target interface, it is essential
that they not contradict one another. For instance, it is a programming error to have an inbound ATMU map
a transaction to the DDR SDRAM memory controller (target interface 0b1111) if the resulting translated local
address is mapped to PCI (target interface 0b0000) by a local access window. Such a programming error may
result in unpredictable system deadlocks.
2.3
All of the memory mapped configuration, control, and status registers in the MPC8533E are contained
within a 1-Mbyte address region. To allow for flexibility, the configuration, control, and status block is
relocatable in the local address space. The local address map location of this register block is controlled
by the configuration, control, and status registers base address register (CCSRBAR), see
“Configuration, Control, and Status Base Address Register (CCSRBAR).”
CCSRBAR is 4 Gbytes–9 Mbytes, or 0x0_FF70_0000.
2.3.1
When the local e500 processor is used to configure CCSR space, the CCSR memory space should typically
be marked as cache-inhibited and guarded.
2-10
Configuration, Control, and Status Register Map
Accessing CCSR Memory from the Local Processor
PCI Inbound ATMU
PCI Express Inbound ATMU
Illegal Interaction Between Inbound ATMUs and Local Access Windows
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The configuration, control, and status window must not overlap a local
access window that maps to the DDR controller. Otherwise, undefined
behavior occurs.
for a detailed description of the PCI inbound ATMU windows.
for a detailed description of the PCI Express inbound ATMU
NOTE
Section 17.3.1.3, “PCI ATMU
The default value for
Section 18.3.5.1, “PCI
Freescale Semiconductor
Section 4.3.1.1.2,