MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 616

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DUART
13.4.3
Local loopback mode is provided for diagnostic testing. The data written to UTHR can be read from the
receiver buffer register (URBR) of the same UART. In this mode, the modem control register UMCR[RTS]
is internally tied to the modem status register UMSR[CTS]. The transmitter SOUT is set to a logic 1 and
the receiver SIN is disconnected. The output of the transmitter shift register is looped back into the receiver
shift register input. The CTS (input signal) is disconnected, RTS is internally connected to CTS, and the
RTS (output signal) becomes inactive. In this diagnostic mode, data that is transmitted is immediately
received. In local loopback mode the transmit and receive data paths of the DUART can be verified. Note
that in local loopback mode, the transmit/receive interrupts are fully operational and can be controlled by
the interrupt enable register (UIER).
13.4.4
The following sections describe framing, parity, and overrun errors which may occur while data is
transferred on the UART bus. Each of the error bits are usually cleared, as described below, when the line
status register (ULSR) is read.
13.4.4.1
When an invalid STOP bit is detected, a framing error occurs and ULSR[FE] is set. Note that only the first
STOP bit is checked. In FIFO mode, ULSR[FE] is set when the character at the top of the FIFO detects a
framing error. An attempt to re-synchronize occurs after a framing error. The UART assumes that the
framing error (due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit
overlapping with the next START bit. ULSR[FE] is cleared when ULSR is read or when a new character
is loaded into the URBR from the receiver shift register.
13.4.4.2
A parity error occurs, and ULSR[PE] is set, when unexpected parity values are encountered while
receiving data. In FIFO mode, ULSR[PE] is set when the character with the error is at the top of the FIFO.
ULSR[PE] is cleared when ULSR is read or when a new character is loaded into the URBR.
13.4.4.3
When a new (overwriting character) STOP bit is detected and the old character is lost, an overrun error
occurs and ULSR[OE] is set. In FIFO mode, ULSR[OE] is set after the receiver FIFO is full (despite the
receiver FIFO trigger level setting) and a new character has been received into the internal receiver shift
register. Data in the FIFO is not overwritten; only the shift register data is overwritten. Therefore, the
interrupt occurs immediately. ULSR[OE] is cleared when ULSR is read.
13.4.5
The UARTs use an alternate mode (FIFO mode) to relieve the processor core from excessive software
overhead. The FIFO control register (UFCR) is used to enable and clear the receiver and transmitter FIFOs
13-22
Local Loopback Mode
Errors
FIFO Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Framing Error
Parity Error
Overrun Error
Freescale Semiconductor