MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1270

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Complete List of Configuration, Control, and Status Registers
B-12
0x2_0000
0x2_0010
0x2_0018
0x2_0020
0x2_0028
0x2_0030
0x2_0038
0x2_0040
0x2_0048
0x2_0100
0x2_0108
0x2_0E00
0x2_0E04
0x2_0E08
0x2_0E20
0x2_0E24
0x2_0E28
0x2_0E40
0x2_0E44
0x2_0E48
0xE38–
0x000–
0x000–
0xE2C
0xFFC
0xFFC
0xFFC
0xE30
0xE34
Offset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PEX_ERR_CAP_R1—PCI Express error capture register 1
PEX_ERR_CAP_R2—PCI Express error capture register 2
PEX_ERR_CAP_R3—PCI Express error capture register 3
Reserved
PCI Express Controller 2 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 2; the
PCI Express Controller 3 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 3; the
L2CTL—L2 control register
L2CEWAR0—L2 cache external write address register 0
L2CEWCR0—L2 cache external write control register 0
L2CEWAR1—L2 cache external write address register 1
L2CEWCR1—L2 cache external write control register 1
L2CEWAR2—L2 cache external write address register 2
L2CEWCR2—L2 cache external write control register 2
L2CEWAR3—L2 cache external write address register 3
L2CEWCR3—L2 cache external write control register 3
L2SRBAR0—L2 memory-mapped SRAM base address
register 0
L2SRBAR1—L2 memory-mapped SRAM base address
register 1
L2ERRINJHI—L2 error injection mask high register
L2ERRINJLO—L2 error injection mask low register
L2ERRINJCTL—L2 error injection tag/ECC control register
L2CAPTDATAHI—L2 error data high capture register
L2CAPTDATALO—L2 error data low capture register
L2CAPTECC—L2 error syndrome register
L2ERRDET—L2 error detect register
L2ERRDIS—L2 error disable register
L2ERRINTEN—L2 error interrupt enable register
PCI Express Controller 3 Memory-Mapped Registers—Block Base Address 0x0_B000
PCI Express Controller 2 Memory-Mapped Registers—Block Base Address 0x0_9000
offsets of PCI Express Controller 2 registers are the same except they have a different block base
address.
offsets of PCI Express Controller 3 registers are the same except they have a different block base
address.
L2/SRAM Memory-Mapped Configuration Registers
Table B-1. Memory Map (continued)
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x2000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
Freescale Semiconductor
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18.3.6.7/18-39
18.3.6.8/18-40
Section/Page
7.3.1.2.1/7-13
7.3.1.2.3/7-14
7.3.1.2.1/7-13
7.3.1.2.3/7-14
7.3.1.2.1/7-13
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7.3.1.2.1/7-13
7.3.1.2.3/7-14
7.3.1.3.1/7-16
7.3.1.3.1/7-16
7.3.1.4.1/7-18
7.3.1.4.1/7-18
7.3.1.4.1/7-18
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.1/7-10