MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 163

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

mapping logic before an access to the new location is seen. To make sure this happens, these guidelines
should be followed:
4.3.1.1.2
Figure 4-1
Table 4-5
Freescale Semiconductor
24–31
8–23
Bits
0–7
Offset 0x0_0000
Reset 0 0
•
•
W
R
CCSRBAR should be updated during initial configuration of the device when only one host or
controller has access to the device.
When the e500 core is writing to CCSRBAR, it should use the following sequence:
Figure 4-1. Configuration, Control, and Status Register Base Address Register (CCSRBAR)
0
defines the bit fields of CCSRBAR.
BASE_ADDR Identifies the16 most-significant address bits of the window used for configuration accesses. The
shows the fields of CCSRBAR.
– If the boot sequencer is being used to initialize, it is recommended that the boot sequencer
– If an external host on PCI is configuring the device, it should set CCSRBAR to the desired
– If the e500 core is initializing the device, it should set CCSRBAR to the desired final
– Read the current value of CCSRBAR using a load word instruction followed by an isync.
– Write the new value to CCSRBAR.
– Perform a load of an address that does not access configuration space or the on-chip SRAM,
– Read the contents of CCSRBAR from its new location, followed by another isync.
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
set CCSRBAR to its desired final location.
final location before the e500 core is released to boot.
location before enabling other I/O devices to access the device.
This forces all accesses to configuration space to complete.
but has an address mapping already in effect (for example, boot ROM). Follow this load
with an isync.
—
—
Configuration, Control, and Status Base Address Register (CCSRBAR)
0
0 0
—
Write reserved, read = 0.
base address is aligned on a 1-Mbyte boundary.
Write reserved, read = 0
0
0 0 0 0 0 0 1 1 1 1 1
7
8
Table 4-5. CCSRBAR Bit Settings
BASE_ADDR
Description
1
1 1 0 1 1 1 0 0 0 0 0 0 0 0
Reset, Clocking, and Initialization
23 24
Access: Read/Write
—
4-5
31