MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1183

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

19.4.1.23 Clock Out Control Register (CLKOCR)
Shown in
the clock out (CLK_OUT) signal.
Table 19-26
Freescale Semiconductor
Offset 0xE_0E00
Reset
Bits
30
31
26–31 CLK_SEL Clock out select
1–25
Bits
W
R
0
ENB
0
Figure
describes the bit settings of CLKOCR.
1
Name
ENB
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
MCK4_DIS
MCK5_DIS
19-23, the CLKOCR contains control bits that select the clock sources to be placed on
Name
Clock out enable
0 CLK_OUT signal is three-stated
1 CLK_OUT signal is driven according to CLKOCR[CLK_SEL]
Reserved
000000 CCB (platform) clock
000001 CCB (platform) clock divided by 2
000010 SYSCLK (echoes SYSCLK input)
000011 SYSCLK divided by 2 (demonstrates
000100 Reserved
000101 Reserved
000110 Reserved
000111 Reserved
001000 Reserved
001001 Reserved
001010 Reserved
001011 Reserved
001100 Reserved
001101 Reserved
001110 Reserved
001111 Reserved
01xx0x Reserved
Table 19-25. DDRCLKDR Field Descriptions (continued)
Figure 19-23. Clock Out Control Register (CLKOCR)
platform PLL lock)
DDR clock 4 disable
0 MCK4 is enabled.
1 MCK4 is disabled.
DDR clock 5 disable
0 MCK5 is enabled.
1 MCK5 is disabled.
Table 19-26. CLKOCR Field Descriptions
—
All zeros
Description
01xx1x Reserved
10x000 Reserved
10x001 Reserved
10x010 PCI bus clock
10x011 PCI bus clock divided by 2
10x100 Reserved
10x101 Reserved
10x110 Reserved
10x111 Logic 0
11x000 Reserved
11x001 Reserved
11x010 Reserved
11x011 Reserved
11x100 Reserved
11x101 Reserved
11x110 Reserved
11x111 Logic 1
Description
25 26
Access: Read/Write
CLK_SEL
Global Utilities
19-23
31