MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 390

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9.6
System software must configure the DDR memory controller, using a memory polling algorithm at system
start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank depths.
System software must also configure the DDR memory controller at system start-up to appropriately
multiplex the row and column address bits for each bank. Refer to row-address configuration in
Section 9.4.1.2, “Chip Select Configuration (CSn_CONFIG).”
these configuration bits.
At system reset, initialization software (boot code) must set up the programmable parameters in the
memory interface configuration registers. See
descriptions of the configuration registers. These parameters are shown in
9-68
Access Error
Notification
Category
TIMING_CFG_3
TIMING_CFG_0
TIMING_CFG_1
TIMING_CFG_2
CSn_CONFIG
CSn_BNDS
Initialization/Application Information
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Single-bit ECC
threshold
Multi-bit ECC
error
Memory select
error
Table 9-53. Memory Interface Configuration Register Initialization Parameters
Error
Chip select memory bounds
Chip select configuration
Extended timing parameters for fields
in TIMING_CFG_1
Timing configuration
Timing configuration
Timing configuration
The number of ECC errors has reached the
threshold specified in the ERR_SBE.
A multi-bit ECC error is detected during a read, or
read-modify-write memory operation.
Read, or write, address does not fall within the
address range of any of the memory banks.
Table 9-52. Memory Controller Errors
Description
Descriptions
Section 9.4.1, “Register Descriptions,”
ODT_WR_CFG
ODT_RD_CFG
RD_TO_PRE
PRETOACT
ACTTOPRE
ACTTORW
CS_n_EN
AP_n_EN
ADD_LAT
WR_LAT
CASLAT
Address multiplexing occurs according to
WWT
RWT
WRT
CPO
RRT
EXT_REFREC
Parameter
The error is reported
via machine check
or critical interrupt if
enabled.
SAn
EAn
Table
WR_DATA_DELAY
ROW_BITS_CS_n
COL_BITS_CS_n
Action
BA_BITS_CS_n
PRE_PD_EXIT
ODT_PD_EXIT
ACT_PD_EXIT
FOUR_ACT
ACTTOACT
MRS_CYC
CKE_PLS
WRTORD
REFREC
WRREC
9-53.
Freescale Semiconductor
for more detailed
The error control
register only logs
read versus write,
not full type
Detect Register
Section/page
9.4.1.1/9-11
9.4.1.2/9-11
9.4.1.3/9-13
9.4.1.4/9-14
9.4.1.5/9-16
9.4.1.6/9-18