MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 595

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Chapter 13
DUART
This chapter describes the dual universal asynchronous receiver/transmitters (DUART). It describes the
functional operation, the DUART initialization sequence, and the programming details for the DUART
registers and features.
13.1
The DUART consists of two universal asynchronous receiver/transmitters (UARTs). The UARTs act
independently; all references to UART refer to one of these receiver/transmitters. Each UART is clocked
by the core complex bus (CCB) clock. The DUART programming model is compatible with the
PC16552D.
The UART interface is point to point, meaning that only two UART devices are attached to the connecting
signals. As shown in
13.1.1
The DUART includes these distinctive features:
Freescale Semiconductor
Receive and transmit buffers
Clear to send (CTS) input port and request to send (RTS) output port for data flow control
16-bit counter for baud rate generation
Interrupt control logic
Full-duplex operation
Programming model compatible with the original PC16450 UART and the PC16550D (an
improved version of the PC16450 that also operates in FIFO mode)
PC16450 register reset values
FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
Serial data encapsulation and decapsulation with standard asynchronous communication bits
(START, STOP, and parity)
Maskable transmit, receive, line status, and modem status interrupts
Software-programmable baud generators that divide the CCB clock by 1 to (2
a 16x clock for the transmitter and receiver engines
Overview
Features
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure
13-1, each UART module consists of the following:
16
– 1) and generate
13-1

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